542 lines
13 KiB
Plaintext
542 lines
13 KiB
Plaintext
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; Options for the Synopsys DesignWare ARC port of the compiler
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;
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; Copyright (C) 2005-2021 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; <http://www.gnu.org/licenses/>.
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HeaderInclude
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config/arc/arc-opts.h
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mbig-endian
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Target RejectNegative Mask(BIG_ENDIAN)
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Compile code for big endian mode.
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mlittle-endian
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Target RejectNegative InverseMask(BIG_ENDIAN)
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Compile code for little endian mode. This is the default.
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mno-cond-exec
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Target RejectNegative Mask(NO_COND_EXEC)
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Disable ARCompact specific pass to generate conditional execution instructions.
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mA6
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Target
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Generate ARCompact 32-bit code for ARC600 processor.
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mARC600
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Target
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Same as -mA6.
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mARC601
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Target
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Generate ARCompact 32-bit code for ARC601 processor.
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mA7
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Target
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Generate ARCompact 32-bit code for ARC700 processor.
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mARC700
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Target
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Same as -mA7.
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mjli-always
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Target Mask(JLI_ALWAYS)
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Force all calls to be made via a jli instruction.
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mmpy-option=
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Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
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-mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
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Enum
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Name(arc_mpy) Type(int)
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EnumValue
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Enum(arc_mpy) String(0) Value(0)
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EnumValue
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Enum(arc_mpy) String(none) Value(0) Canonical
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EnumValue
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Enum(arc_mpy) String(1) Value(1)
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EnumValue
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Enum(arc_mpy) String(w) Value(1) Canonical
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EnumValue
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Enum(arc_mpy) String(2) Value(2)
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EnumValue
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Enum(arc_mpy) String(mpy) Value(2)
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EnumValue
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Enum(arc_mpy) String(wlh1) Value(2) Canonical
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EnumValue
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Enum(arc_mpy) String(3) Value(3)
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EnumValue
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Enum(arc_mpy) String(wlh2) Value(3) Canonical
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EnumValue
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Enum(arc_mpy) String(4) Value(4)
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EnumValue
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Enum(arc_mpy) String(wlh3) Value(4) Canonical
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EnumValue
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Enum(arc_mpy) String(5) Value(5)
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EnumValue
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Enum(arc_mpy) String(wlh4) Value(5) Canonical
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EnumValue
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Enum(arc_mpy) String(6) Value(6)
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EnumValue
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Enum(arc_mpy) String(wlh5) Value(6) Canonical
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EnumValue
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Enum(arc_mpy) String(7) Value(7)
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EnumValue
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Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
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EnumValue
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Enum(arc_mpy) String(8) Value(8)
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EnumValue
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Enum(arc_mpy) String(plus_macd) Value(8) Canonical
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EnumValue
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Enum(arc_mpy) String(9) Value(9)
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EnumValue
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Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
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mdiv-rem
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Target Mask(DIVREM)
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Enable DIV-REM instructions for ARCv2.
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mcode-density
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Target Mask(CODE_DENSITY)
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Enable code density instructions for ARCv2.
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mmixed-code
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Target Mask(MIXED_CODE_SET)
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Tweak register allocation to help 16-bit instruction generation.
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; originally this was:
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;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
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; but we do that without -mmixed-code, too, it's just a different instruction
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; count / size tradeoff.
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; We use an explict definition for the negative form because that is the
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; actually interesting option, and we want that to have its own comment.
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mvolatile-cache
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Target RejectNegative Mask(VOLATILE_CACHE_SET)
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Use ordinarily cached memory accesses for volatile references.
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mno-volatile-cache
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Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
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Enable cache bypass for volatile references.
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mbarrel-shifter
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Target Mask(BARREL_SHIFTER)
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Generate instructions supported by barrel shifter.
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mnorm
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Target Mask(NORM_SET)
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Generate norm instruction.
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mswap
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Target Mask(SWAP_SET)
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Generate swap instruction.
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mmul64
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Target Mask(MUL64_SET)
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Generate mul64 and mulu64 instructions.
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mno-mpy
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Target Mask(NOMPY_SET) Warn(%qs is deprecated)
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Do not generate mpy instructions for ARC700.
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mea
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Target Mask(EA_SET)
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Generate extended arithmetic instructions, only valid for ARC700.
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msoft-float
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Target Mask(0)
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Dummy flag. This is the default unless FPX switches are provided explicitly.
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mlong-calls
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Target Mask(LONG_CALLS_SET)
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Generate call insns as register indirect calls.
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mno-brcc
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Target Mask(NO_BRCC_SET)
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Do no generate BRcc instructions in arc_reorg.
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msdata
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Target InverseMask(NO_SDATA_SET)
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Generate sdata references. This is the default, unless you compile for PIC.
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mmillicode
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Target Mask(MILLICODE_THUNK_SET)
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Generate millicode thunks.
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mspfp
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Target Mask(SPFP_COMPACT_SET)
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FPX: Generate Single Precision FPX (compact) instructions.
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mspfp-compact
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Target Mask(SPFP_COMPACT_SET) MaskExists
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FPX: Generate Single Precision FPX (compact) instructions.
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mspfp-fast
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Target Mask(SPFP_FAST_SET)
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FPX: Generate Single Precision FPX (fast) instructions.
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margonaut
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Target Mask(ARGONAUT_SET)
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FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
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mdpfp
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Target Mask(DPFP_COMPACT_SET)
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FPX: Generate Double Precision FPX (compact) instructions.
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mdpfp-compact
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Target Mask(DPFP_COMPACT_SET) MaskExists
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FPX: Generate Double Precision FPX (compact) instructions.
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mdpfp-fast
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Target Mask(DPFP_FAST_SET)
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FPX: Generate Double Precision FPX (fast) instructions.
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mno-dpfp-lrsr
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Target Mask(DPFP_DISABLE_LRSR)
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Disable LR and SR instructions from using FPX extension aux registers.
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msimd
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Target Mask(SIMD_SET)
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Enable generation of ARC SIMD instructions via target-specific builtins.
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mcpu=
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Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
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-mcpu=CPU Compile code for ARC variant CPU.
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msize-level=
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Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
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Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
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misize
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Target PchIgnore Var(TARGET_DUMPISIZE)
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Annotate assembler instructions with estimated addresses.
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mmultcost=
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Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
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Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
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mtune=
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Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE)
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-mtune=TUNE Tune code for given ARC variant.
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Enum
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Name(arc_tune_attr) Type(int)
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EnumValue
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Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600)
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EnumValue
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Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600)
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EnumValue
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Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX)
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EnumValue
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Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD)
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EnumValue
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Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC)
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EnumValue
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Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC)
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EnumValue
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Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC)
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EnumValue
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Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3)
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mindexed-loads
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Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
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Enable the use of indexed loads.
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mauto-modify-reg
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Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
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Enable the use of pre/post modify with register displacement.
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mmul32x16
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Target Mask(MULMAC_32BY16_SET)
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Generate 32x16 multiply and mac instructions.
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; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
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; alas, basic-block.h is not included in options.c .
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munalign-prob-threshold=
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Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
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Set probability threshold for unaligning branches.
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mmedium-calls
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Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
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Don't use less than 25 bit addressing range for calls.
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mannotate-align
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Target Var(TARGET_ANNOTATE_ALIGN)
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Explain what alignment considerations lead to the decision to make an insn short or long.
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malign-call
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Target Var(TARGET_ALIGN_CALL)
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Do alignment optimizations for call instructions.
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mRcq
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Target Var(TARGET_Rcq)
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Enable Rcq constraint handling - most short code generation depends on this.
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mRcw
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Target Var(TARGET_Rcw)
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Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
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mearly-cbranchsi
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Target Var(TARGET_EARLY_CBRANCHSI)
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Enable pre-reload use of cbranchsi pattern.
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mbbit-peephole
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Target Var(TARGET_BBIT_PEEPHOLE)
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Enable bbit peephole2.
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mcase-vector-pcrel
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Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
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Use pc-relative switch case tables - this enables case table shortening.
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mcompact-casesi
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Target Warn(%qs is deprecated)
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Enable compact casesi pattern.
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mq-class
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Target Warn(%qs is deprecated)
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Enable 'q' instruction alternatives.
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mexpand-adddi
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Target Warn(%qs is deprecated)
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Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
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; Flags used by the assembler, but for which we define preprocessor
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; macro symbols as well.
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mcrc
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Target Warn(%qs is deprecated)
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Enable variable polynomial CRC extension.
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mdsp-packa
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Target Warn(%qs is deprecated)
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Enable DSP 3.1 Pack A extensions.
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mdvbf
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Target Warn(%qs is deprecated)
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Enable dual viterbi butterfly extension.
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mmac-d16
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Target Undocumented Warn(%qs is deprecated)
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mmac-24
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Target Undocumented Warn(%qs is deprecated)
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mtelephony
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Target RejectNegative Warn(%qs is deprecated)
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Enable Dual and Single Operand Instructions for Telephony.
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mxy
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Target
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Enable XY Memory extension (DSP version 3).
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; ARC700 4.10 extension instructions
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mlock
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Target
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Enable Locked Load/Store Conditional extension.
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mswape
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Target
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Enable swap byte ordering extension instruction.
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mrtsc
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Target Warn(%qs is deprecated)
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Enable 64-bit Time-Stamp Counter extension instruction.
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EB
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Target
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Pass -EB option through to linker.
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EL
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Target
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Pass -EL option through to linker.
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marclinux
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Target
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Pass -marclinux option through to linker.
|
||
|
|
|
||
|
|
marclinux_prof
|
||
|
|
Target
|
||
|
|
Pass -marclinux_prof option through to linker.
|
||
|
|
|
||
|
|
;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
|
||
|
|
mlra
|
||
|
|
Target Var(arc_lra_flag) Init(1) Save
|
||
|
|
Use LRA instead of reload.
|
||
|
|
|
||
|
|
mlra-priority-none
|
||
|
|
Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
|
||
|
|
Don't indicate any priority with TARGET_REGISTER_PRIORITY.
|
||
|
|
|
||
|
|
mlra-priority-compact
|
||
|
|
Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
|
||
|
|
Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
|
||
|
|
|
||
|
|
mlra-priority-noncompact
|
||
|
|
Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
|
||
|
|
Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
|
||
|
|
|
||
|
|
; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
|
||
|
|
|
||
|
|
mEA
|
||
|
|
Target
|
||
|
|
|
||
|
|
multcost=
|
||
|
|
Target RejectNegative Joined
|
||
|
|
|
||
|
|
matomic
|
||
|
|
Target Mask(ATOMIC)
|
||
|
|
Enable atomic instructions.
|
||
|
|
|
||
|
|
mll64
|
||
|
|
Target Mask(LL64)
|
||
|
|
Enable double load/store instructions for ARC HS.
|
||
|
|
|
||
|
|
mfpu=
|
||
|
|
Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
|
||
|
|
Specify the name of the target floating point configuration.
|
||
|
|
|
||
|
|
Enum
|
||
|
|
Name(arc_fpu) Type(int)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
|
||
|
|
|
||
|
|
mtp-regno=
|
||
|
|
Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
|
||
|
|
Specify thread pointer register number.
|
||
|
|
|
||
|
|
mtp-regno=none
|
||
|
|
Target RejectNegative Var(arc_tp_regno,-1)
|
||
|
|
|
||
|
|
mbitops
|
||
|
|
Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
|
||
|
|
Enable use of NPS400 bit operations.
|
||
|
|
|
||
|
|
mcmem
|
||
|
|
Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
|
||
|
|
Enable use of NPS400 xld/xst extension.
|
||
|
|
|
||
|
|
munaligned-access
|
||
|
|
Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
|
||
|
|
Enable unaligned word and halfword accesses to packed data.
|
||
|
|
|
||
|
|
mirq-ctrl-saved=
|
||
|
|
Target RejectNegative Joined Var(arc_deferred_options) Defer
|
||
|
|
Specifies the registers that the processor saves on an interrupt entry and exit.
|
||
|
|
|
||
|
|
mrgf-banked-regs=
|
||
|
|
Target RejectNegative Joined Var(arc_deferred_options) Defer
|
||
|
|
Specifies the number of registers replicated in second register bank on entry to fast interrupt.
|
||
|
|
|
||
|
|
mlpc-width=
|
||
|
|
Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
|
||
|
|
Sets LP_COUNT register width. Possible values are 8, 16, 20, 24, 28, and 32.
|
||
|
|
|
||
|
|
Enum
|
||
|
|
Name(arc_lpc) Type(int)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_lpc) String(8) Value(8)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_lpc) String(16) Value(16)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_lpc) String(20) Value(20)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_lpc) String(24) Value(24)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_lpc) String(28) Value(28)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(arc_lpc) String(32) Value(32)
|
||
|
|
|
||
|
|
mrf16
|
||
|
|
Target Mask(RF16)
|
||
|
|
Enable 16-entry register file.
|
||
|
|
|
||
|
|
mbranch-index
|
||
|
|
Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
|
||
|
|
Enable use of BI/BIH instructions when available.
|
||
|
|
|
||
|
|
mcode-density-frame
|
||
|
|
Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
|
||
|
|
Enable ENTER_S and LEAVE_S opcodes for ARCv2.
|