101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
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/* PLT fixups. Sparc 32-bit version.
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Copyright (C) 1996-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _DL_PLT_H
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#define _DL_PLT_H
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/* Some SPARC opcodes we need to use for self-modifying code. */
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#define OPCODE_NOP 0x01000000 /* nop */
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#define OPCODE_CALL 0x40000000 /* call ?; add PC-rel word address */
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#define OPCODE_SETHI_G1 0x03000000 /* sethi ?, %g1; add value>>10 */
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#define OPCODE_JMP_G1 0x81c06000 /* jmp %g1+?; add lo 10 bits of value */
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#define OPCODE_SAVE_SP 0x9de3bfa8 /* save %sp, -(16+6)*4, %sp */
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#define OPCODE_BA 0x30800000 /* b,a ?; add PC-rel word address */
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#define OPCODE_BA_PT 0x30480000 /* ba,a,pt %icc, ?; add PC-rel word address */
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static inline __attribute__ ((always_inline)) Elf32_Addr
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sparc_fixup_plt (const Elf32_Rela *reloc, Elf32_Addr *reloc_addr,
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Elf32_Addr value, int t, int do_flush)
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{
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Elf32_Sword disp;
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/* 't' is '0' if we are resolving this PLT entry for RTLD bootstrap,
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in which case we'll be resolving all PLT entries and thus can
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optimize by overwriting instructions starting at the first PLT entry
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instruction and we need not be mindful of thread safety.
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Otherwise, 't' is '1'. */
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reloc_addr += t;
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disp = value - (Elf32_Addr) reloc_addr;
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if (disp >= -0x800000 && disp < 0x800000)
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{
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unsigned int insn = OPCODE_BA | ((disp >> 2) & 0x3fffff);
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#ifdef __sparc_v9__
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/* On V9 we can do even better by using a branch with
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prediction if we fit into the even smaller 19-bit
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displacement field. */
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if (disp >= -0x100000 && disp < 0x100000)
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insn = OPCODE_BA_PT | ((disp >> 2) & 0x07ffff);
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#endif
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/* Even if we are writing just a single branch, we must not
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ignore the 't' offset. Consider a case where we have some
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PLT slots which can be optimized into a single branch and
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some which cannot. Then we can end up with a PLT which looks
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like:
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PLT4.0: sethi %(PLT_4_INDEX), %g1
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sethi %(fully_resolved_sym_4), %g1
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jmp %g1 + %lo(fully_resolved_sym_4)
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PLT5.0: ba,a fully_resolved_sym_5
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ba,a PLT0.0
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...
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The delay slot of that jmp must always be either a sethi to
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%g1 or a nop. But if we try to place this displacement
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branch there, PLT4.0 will jump to fully_resolved_sym_4 for 1
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instruction and then go immediately to
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fully_resolved_sym_5. */
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reloc_addr[0] = insn;
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if (do_flush)
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__asm __volatile ("flush %0" : : "r"(reloc_addr));
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}
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else
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{
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/* For thread safety, write the instructions from the bottom and
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flush before we overwrite the critical "b,a". This of course
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need not be done during bootstrapping, since there are no threads.
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But we also can't tell if we _can_ use flush, so don't. */
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reloc_addr[1] = OPCODE_JMP_G1 | (value & 0x3ff);
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if (do_flush)
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__asm __volatile ("flush %0+4" : : "r"(reloc_addr));
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reloc_addr[0] = OPCODE_SETHI_G1 | (value >> 10);
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if (do_flush)
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__asm __volatile ("flush %0" : : "r"(reloc_addr));
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}
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return value;
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}
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#endif /* dl-plt.h */
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