322 lines
12 KiB
C
322 lines
12 KiB
C
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/* Internal libc stuff for floating point environment routines.
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Copyright (C) 1997-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _FENV_LIBC_H
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#define _FENV_LIBC_H 1
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#include <fenv.h>
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#include <ldsodefs.h>
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#include <sysdep.h>
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extern const fenv_t *__fe_nomask_env_priv (void);
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extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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/* If the old env had any enabled exceptions and the new env has no enabled
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exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
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FPU to run faster because it always takes the default action and can not
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generate SIGFPE. */
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#define __TEST_AND_ENTER_NON_STOP(old, new) \
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do { \
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if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \
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(void) __fe_mask_env (); \
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} while (0)
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/* If the old env has no enabled exceptions and the new env has any enabled
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exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
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hardware into "precise mode" and may cause the FPU to run slower on some
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hardware. */
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#define __TEST_AND_EXIT_NON_STOP(old, new) \
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do { \
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if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \
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(void) __fe_nomask_env_priv (); \
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} while (0)
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/* The sticky bits in the FPSCR indicating exceptions have occurred. */
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#define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
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/* Equivalent to fegetenv, but returns a fenv_t instead of taking a
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pointer. */
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#define fegetenv_register() __builtin_mffs()
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/* Equivalent to fegetenv_register, but only returns bits for
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status, exception enables, and mode.
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Nicely, it turns out that the 'mffsl' instruction will decode to
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'mffs' on architectures older than "power9" because the additional
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bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset
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of 'mffsl'. */
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#define fegetenv_control() \
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({register double __fr; \
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__asm__ __volatile__ ( \
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".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
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: "=f" (__fr)); \
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__fr; \
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})
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#define __fe_mffscrn(rn) \
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({register fenv_union_t __fr; \
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if (__builtin_constant_p (rn)) \
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__asm__ __volatile__ ( \
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".machine push; .machine \"power9\"; mffscrni %0,%1; .machine pop" \
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: "=f" (__fr.fenv) : "n" (rn)); \
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else \
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{ \
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__fr.l = (rn); \
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__asm__ __volatile__ ( \
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".machine push; .machine \"power9\"; mffscrn %0,%1; .machine pop" \
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: "=f" (__fr.fenv) : "f" (__fr.fenv)); \
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} \
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__fr.fenv; \
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})
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/* Like fegetenv_control, but also sets the rounding mode. */
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#ifdef _ARCH_PWR9
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#define fegetenv_and_set_rn(rn) __fe_mffscrn (rn)
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#else
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/* 'mffscrn' will decode to 'mffs' on ARCH < 3_00, which is still necessary
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but not sufficient, because it does not set the rounding mode.
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Explicitly set the rounding mode when 'mffscrn' actually doesn't. */
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#define fegetenv_and_set_rn(rn) \
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({register fenv_union_t __fr; \
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__fr.fenv = __fe_mffscrn (rn); \
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if (__glibc_unlikely (!(GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))) \
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__fesetround_inline (rn); \
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__fr.fenv; \
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})
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#endif
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/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
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#define fesetenv_register(env) \
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do { \
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double d = (env); \
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if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
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asm volatile (".machine push; " \
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".machine \"power6\"; " \
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"mtfsf 0xff,%0,1,0; " \
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".machine pop" : : "f" (d)); \
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else \
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__builtin_mtfsf (0xff, d); \
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} while(0)
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/* Set the last 2 nibbles of the FPSCR, which contain the
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exception enables and the rounding mode.
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'fegetenv_control' retrieves these bits by reading the FPSCR. */
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#define fesetenv_control(env) __builtin_mtfsf (0b00000011, (env));
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/* This very handy macro:
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- Sets the rounding mode to 'round to nearest';
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- Sets the processor into IEEE mode; and
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- Prevents exceptions from being raised for inexact results.
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These things happen to be exactly what you need for typical elementary
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functions. */
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#define relax_fenv_state() \
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do { \
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if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
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asm volatile (".machine push; .machine \"power6\"; " \
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"mtfsfi 7,0,1; .machine pop"); \
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asm volatile ("mtfsfi 7,0"); \
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} while(0)
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/* Set/clear a particular FPSCR bit (for instance,
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reset_fpscr_bit(FPSCR_VE);
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prevents INVALID exceptions from being raised). */
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#define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "n"(x))
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#define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "n"(x))
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typedef union
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{
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fenv_t fenv;
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unsigned long long l;
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} fenv_union_t;
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static inline int
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__fesetround_inline (int round)
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{
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#ifdef _ARCH_PWR9
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__fe_mffscrn (round);
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#else
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if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
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__fe_mffscrn (round);
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else if ((unsigned int) round < 2)
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{
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asm volatile ("mtfsb0 30");
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if ((unsigned int) round == 0)
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asm volatile ("mtfsb0 31");
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else
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asm volatile ("mtfsb1 31");
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}
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else
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{
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asm volatile ("mtfsb1 30");
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if ((unsigned int) round == 2)
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asm volatile ("mtfsb0 31");
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else
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asm volatile ("mtfsb1 31");
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}
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#endif
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return 0;
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}
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/* Same as __fesetround_inline, however without runtime check to use DFP
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mtfsfi syntax (as relax_fenv_state) or if round value is valid. */
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static inline void
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__fesetround_inline_nocheck (const int round)
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{
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#ifdef _ARCH_PWR9
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__fe_mffscrn (round);
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#else
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if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
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__fe_mffscrn (round);
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else
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asm volatile ("mtfsfi 7,%0" : : "n" (round));
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#endif
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}
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#define FPSCR_MASK(bit) (1 << (31 - (bit)))
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/* Definitions of all the FPSCR bit numbers */
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enum {
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FPSCR_FX = 0, /* exception summary */
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#define FPSCR_FX_MASK (FPSCR_MASK (FPSCR_FX))
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FPSCR_FEX, /* enabled exception summary */
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#define FPSCR_FEX_MASK (FPSCR_MASK FPSCR_FEX))
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FPSCR_VX, /* invalid operation summary */
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#define FPSCR_VX_MASK (FPSCR_MASK (FPSCR_VX))
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FPSCR_OX, /* overflow */
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#define FPSCR_OX_MASK (FPSCR_MASK (FPSCR_OX))
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FPSCR_UX, /* underflow */
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#define FPSCR_UX_MASK (FPSCR_MASK (FPSCR_UX))
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FPSCR_ZX, /* zero divide */
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#define FPSCR_ZX_MASK (FPSCR_MASK (FPSCR_ZX))
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FPSCR_XX, /* inexact */
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#define FPSCR_XX_MASK (FPSCR_MASK (FPSCR_XX))
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FPSCR_VXSNAN, /* invalid operation for sNaN */
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#define FPSCR_VXSNAN_MASK (FPSCR_MASK (FPSCR_VXSNAN))
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FPSCR_VXISI, /* invalid operation for Inf-Inf */
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#define FPSCR_VXISI_MASK (FPSCR_MASK (FPSCR_VXISI))
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FPSCR_VXIDI, /* invalid operation for Inf/Inf */
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#define FPSCR_VXIDI_MASK (FPSCR_MASK (FPSCR_VXIDI))
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FPSCR_VXZDZ, /* invalid operation for 0/0 */
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#define FPSCR_VXZDZ_MASK (FPSCR_MASK (FPSCR_VXZDZ))
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FPSCR_VXIMZ, /* invalid operation for Inf*0 */
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#define FPSCR_VXIMZ_MASK (FPSCR_MASK (FPSCR_VXIMZ))
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FPSCR_VXVC, /* invalid operation for invalid compare */
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#define FPSCR_VXVC_MASK (FPSCR_MASK (FPSCR_VXVC))
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FPSCR_FR, /* fraction rounded [fraction was incremented by round] */
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#define FPSCR_FR_MASK (FPSCR_MASK (FPSCR_FR))
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FPSCR_FI, /* fraction inexact */
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#define FPSCR_FI_MASK (FPSCR_MASK (FPSCR_FI))
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FPSCR_FPRF_C, /* result class descriptor */
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#define FPSCR_FPRF_C_MASK (FPSCR_MASK (FPSCR_FPRF_C))
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FPSCR_FPRF_FL, /* result less than (usually, less than 0) */
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#define FPSCR_FPRF_FL_MASK (FPSCR_MASK (FPSCR_FPRF_FL))
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FPSCR_FPRF_FG, /* result greater than */
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#define FPSCR_FPRF_FG_MASK (FPSCR_MASK (FPSCR_FPRF_FG))
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FPSCR_FPRF_FE, /* result equal to */
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#define FPSCR_FPRF_FE_MASK (FPSCR_MASK (FPSCR_FPRF_FE))
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FPSCR_FPRF_FU, /* result unordered */
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#define FPSCR_FPRF_FU_MASK (FPSCR_MASK (FPSCR_FPRF_FU))
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FPSCR_20, /* reserved */
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FPSCR_VXSOFT, /* invalid operation set by software */
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#define FPSCR_VXSOFT_MASK (FPSCR_MASK (FPSCR_VXSOFT))
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FPSCR_VXSQRT, /* invalid operation for square root */
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#define FPSCR_VXSQRT_MASK (FPSCR_MASK (FPSCR_VXSQRT))
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FPSCR_VXCVI, /* invalid operation for invalid integer convert */
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#define FPSCR_VXCVI_MASK (FPSCR_MASK (FPSCR_VXCVI))
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FPSCR_VE, /* invalid operation exception enable */
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#define FPSCR_VE_MASK (FPSCR_MASK (FPSCR_VE))
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FPSCR_OE, /* overflow exception enable */
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#define FPSCR_OE_MASK (FPSCR_MASK (FPSCR_OE))
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FPSCR_UE, /* underflow exception enable */
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#define FPSCR_UE_MASK (FPSCR_MASK (FPSCR_UE))
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FPSCR_ZE, /* zero divide exception enable */
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#define FPSCR_ZE_MASK (FPSCR_MASK (FPSCR_ZE))
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FPSCR_XE, /* inexact exception enable */
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#define FPSCR_XE_MASK (FPSCR_MASK (FPSCR_XE))
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#ifdef _ARCH_PWR6
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FPSCR_29, /* Reserved in ISA 2.05 */
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#define FPSCR_NI_MASK (FPSCR_MASK (FPSCR_29))
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#else
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FPSCR_NI, /* non-IEEE mode (typically, no denormalised numbers) */
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#define FPSCR_NI_MASK (FPSCR_MASK (FPSCR_NI))
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#endif /* _ARCH_PWR6 */
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/* the remaining two least-significant bits keep the rounding mode */
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FPSCR_RN_hi,
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#define FPSCR_RN_hi_MASK (FPSCR_MASK (FPSCR_RN_hi))
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FPSCR_RN_lo
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#define FPSCR_RN_lo_MASK (FPSCR_MASK (FPSCR_RN_lo))
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};
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#define FPSCR_RN_MASK (FPSCR_RN_hi_MASK|FPSCR_RN_lo_MASK)
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#define FPSCR_ENABLES_MASK \
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(FPSCR_VE_MASK|FPSCR_OE_MASK|FPSCR_UE_MASK|FPSCR_ZE_MASK|FPSCR_XE_MASK)
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#define FPSCR_BASIC_EXCEPTIONS_MASK \
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(FPSCR_VX_MASK|FPSCR_OX_MASK|FPSCR_UX_MASK|FPSCR_ZX_MASK|FPSCR_XX_MASK)
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#define FPSCR_EXCEPTIONS_MASK (FPSCR_BASIC_EXCEPTIONS_MASK| \
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FPSCR_VXSNAN_MASK|FPSCR_VXISI_MASK|FPSCR_VXIDI_MASK|FPSCR_VXZDZ_MASK| \
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FPSCR_VXIMZ_MASK|FPSCR_VXVC_MASK|FPSCR_VXSOFT_MASK|FPSCR_VXSQRT_MASK| \
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FPSCR_VXCVI_MASK)
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#define FPSCR_FPRF_MASK \
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(FPSCR_FPRF_C_MASK|FPSCR_FPRF_FL_MASK|FPSCR_FPRF_FG_MASK| \
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FPSCR_FPRF_FE_MASK|FPSCR_FPRF_FU_MASK)
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#define FPSCR_CONTROL_MASK (FPSCR_ENABLES_MASK|FPSCR_NI_MASK|FPSCR_RN_MASK)
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#define FPSCR_STATUS_MASK (FPSCR_FR_MASK|FPSCR_FI_MASK|FPSCR_FPRF_MASK)
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/* The bits in the FENV(1) ABI for exceptions correspond one-to-one with bits
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in the FPSCR, albeit shifted to different but corresponding locations.
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Similarly, the exception indicator bits in the FPSCR correspond one-to-one
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with the exception enable bits. It is thus possible to map the FENV(1)
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exceptions directly to the FPSCR enables with a simple mask and shift,
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and vice versa. */
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#define FPSCR_EXCEPT_TO_ENABLE_SHIFT 22
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static inline int
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fenv_reg_to_exceptions (unsigned long long l)
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{
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return (((int)l) & FPSCR_ENABLES_MASK) << FPSCR_EXCEPT_TO_ENABLE_SHIFT;
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}
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static inline unsigned long long
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fenv_exceptions_to_reg (int excepts)
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{
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return (unsigned long long)
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(excepts & FE_ALL_EXCEPT) >> FPSCR_EXCEPT_TO_ENABLE_SHIFT;
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}
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#ifdef _ARCH_PWR6
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/* Not supported in ISA 2.05. Provided for source compat only. */
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# define FPSCR_NI 29
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#endif /* _ARCH_PWR6 */
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/* This operation (i) sets the appropriate FPSCR bits for its
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parameter, (ii) converts sNaN to the corresponding qNaN, and (iii)
|
||
|
|
otherwise passes its parameter through unchanged (in particular, -0
|
||
|
|
and +0 stay as they were). The `obvious' way to do this is optimised
|
||
|
|
out by gcc. */
|
||
|
|
#define f_wash(x) \
|
||
|
|
({ double d; asm volatile ("fmul %0,%1,%2" \
|
||
|
|
: "=f"(d) \
|
||
|
|
: "f" (x), "f"((float)1.0)); d; })
|
||
|
|
#define f_washf(x) \
|
||
|
|
({ float f; asm volatile ("fmuls %0,%1,%2" \
|
||
|
|
: "=f"(f) \
|
||
|
|
: "f" (x), "f"((float)1.0)); f; })
|
||
|
|
|
||
|
|
#endif /* fenv_libc.h */
|