340 lines
11 KiB
C
340 lines
11 KiB
C
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/* Copyright (C) 2003-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <stdint.h>
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#define __HAVE_64B_ATOMICS 1
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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/* XXX Is this actually correct? */
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#define ATOMIC_EXCHANGE_USES_CAS 1
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#define __MB " mb\n"
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/* Compare and exchange. For all of the "xxx" routines, we expect a
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"__prev" and a "__cmp" variable to be provided by the enclosing scope,
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in which values are returned. */
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#define __arch_compare_and_exchange_xxx_8_int(mem, new, old, mb1, mb2) \
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({ \
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unsigned long __tmp, __snew, __addr64; \
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__asm__ __volatile__ ( \
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mb1 \
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" andnot %[__addr8],7,%[__addr64]\n" \
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" insbl %[__new],%[__addr8],%[__snew]\n" \
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"1: ldq_l %[__tmp],0(%[__addr64])\n" \
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" extbl %[__tmp],%[__addr8],%[__prev]\n" \
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" cmpeq %[__prev],%[__old],%[__cmp]\n" \
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" beq %[__cmp],2f\n" \
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" mskbl %[__tmp],%[__addr8],%[__tmp]\n" \
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" or %[__snew],%[__tmp],%[__tmp]\n" \
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" stq_c %[__tmp],0(%[__addr64])\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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"2:" \
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: [__prev] "=&r" (__prev), \
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[__snew] "=&r" (__snew), \
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[__tmp] "=&r" (__tmp), \
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[__cmp] "=&r" (__cmp), \
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[__addr64] "=&r" (__addr64) \
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: [__addr8] "r" (mem), \
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[__old] "Ir" ((uint64_t)(uint8_t)(uint64_t)(old)), \
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[__new] "r" (new) \
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: "memory"); \
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})
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#define __arch_compare_and_exchange_xxx_16_int(mem, new, old, mb1, mb2) \
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({ \
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unsigned long __tmp, __snew, __addr64; \
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__asm__ __volatile__ ( \
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mb1 \
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" andnot %[__addr16],7,%[__addr64]\n" \
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" inswl %[__new],%[__addr16],%[__snew]\n" \
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"1: ldq_l %[__tmp],0(%[__addr64])\n" \
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" extwl %[__tmp],%[__addr16],%[__prev]\n" \
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" cmpeq %[__prev],%[__old],%[__cmp]\n" \
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" beq %[__cmp],2f\n" \
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" mskwl %[__tmp],%[__addr16],%[__tmp]\n" \
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" or %[__snew],%[__tmp],%[__tmp]\n" \
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" stq_c %[__tmp],0(%[__addr64])\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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"2:" \
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: [__prev] "=&r" (__prev), \
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[__snew] "=&r" (__snew), \
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[__tmp] "=&r" (__tmp), \
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[__cmp] "=&r" (__cmp), \
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[__addr64] "=&r" (__addr64) \
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: [__addr16] "r" (mem), \
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[__old] "Ir" ((uint64_t)(uint16_t)(uint64_t)(old)), \
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[__new] "r" (new) \
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: "memory"); \
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})
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#define __arch_compare_and_exchange_xxx_32_int(mem, new, old, mb1, mb2) \
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({ \
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__asm__ __volatile__ ( \
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mb1 \
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"1: ldl_l %[__prev],%[__mem]\n" \
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" cmpeq %[__prev],%[__old],%[__cmp]\n" \
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" beq %[__cmp],2f\n" \
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" mov %[__new],%[__cmp]\n" \
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" stl_c %[__cmp],%[__mem]\n" \
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" beq %[__cmp],1b\n" \
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mb2 \
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"2:" \
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: [__prev] "=&r" (__prev), \
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[__cmp] "=&r" (__cmp) \
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: [__mem] "m" (*(mem)), \
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[__old] "Ir" ((uint64_t)(int32_t)(uint64_t)(old)), \
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[__new] "Ir" (new) \
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: "memory"); \
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})
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#define __arch_compare_and_exchange_xxx_64_int(mem, new, old, mb1, mb2) \
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({ \
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__asm__ __volatile__ ( \
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mb1 \
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"1: ldq_l %[__prev],%[__mem]\n" \
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" cmpeq %[__prev],%[__old],%[__cmp]\n" \
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" beq %[__cmp],2f\n" \
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" mov %[__new],%[__cmp]\n" \
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" stq_c %[__cmp],%[__mem]\n" \
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" beq %[__cmp],1b\n" \
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mb2 \
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"2:" \
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: [__prev] "=&r" (__prev), \
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[__cmp] "=&r" (__cmp) \
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: [__mem] "m" (*(mem)), \
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[__old] "Ir" ((uint64_t)(old)), \
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[__new] "Ir" (new) \
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: "memory"); \
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})
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/* For all "bool" routines, we return FALSE if exchange succesful. */
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#define __arch_compare_and_exchange_bool_8_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_8_int(mem, new, old, mb1, mb2); \
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!__cmp; })
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#define __arch_compare_and_exchange_bool_16_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_16_int(mem, new, old, mb1, mb2); \
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!__cmp; })
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#define __arch_compare_and_exchange_bool_32_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_32_int(mem, new, old, mb1, mb2); \
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!__cmp; })
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#define __arch_compare_and_exchange_bool_64_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_64_int(mem, new, old, mb1, mb2); \
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!__cmp; })
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/* For all "val" routines, return the old value whether exchange
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successful or not. */
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#define __arch_compare_and_exchange_val_8_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_8_int(mem, new, old, mb1, mb2); \
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(typeof (*mem))__prev; })
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#define __arch_compare_and_exchange_val_16_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_16_int(mem, new, old, mb1, mb2); \
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(typeof (*mem))__prev; })
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#define __arch_compare_and_exchange_val_32_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_32_int(mem, new, old, mb1, mb2); \
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(typeof (*mem))__prev; })
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#define __arch_compare_and_exchange_val_64_int(mem, new, old, mb1, mb2) \
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({ unsigned long __prev; int __cmp; \
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__arch_compare_and_exchange_xxx_64_int(mem, new, old, mb1, mb2); \
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(typeof (*mem))__prev; })
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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#define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, "", __MB)
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#define atomic_compare_and_exchange_val_acq(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, "", __MB)
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/* Compare and exchange with "release" semantics, ie barrier before. */
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#define atomic_compare_and_exchange_val_rel(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __MB, "")
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/* Atomically store value and return the previous value. */
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#define __arch_exchange_8_int(mem, value, mb1, mb2) \
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({ \
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unsigned long __tmp, __addr64, __sval; __typeof(*mem) __ret; \
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__asm__ __volatile__ ( \
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mb1 \
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" andnot %[__addr8],7,%[__addr64]\n" \
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" insbl %[__value],%[__addr8],%[__sval]\n" \
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"1: ldq_l %[__tmp],0(%[__addr64])\n" \
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" extbl %[__tmp],%[__addr8],%[__ret]\n" \
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" mskbl %[__tmp],%[__addr8],%[__tmp]\n" \
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" or %[__sval],%[__tmp],%[__tmp]\n" \
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" stq_c %[__tmp],0(%[__addr64])\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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: [__ret] "=&r" (__ret), \
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[__sval] "=&r" (__sval), \
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[__tmp] "=&r" (__tmp), \
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[__addr64] "=&r" (__addr64) \
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: [__addr8] "r" (mem), \
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[__value] "r" (value) \
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: "memory"); \
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__ret; })
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#define __arch_exchange_16_int(mem, value, mb1, mb2) \
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({ \
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unsigned long __tmp, __addr64, __sval; __typeof(*mem) __ret; \
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__asm__ __volatile__ ( \
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mb1 \
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" andnot %[__addr16],7,%[__addr64]\n" \
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" inswl %[__value],%[__addr16],%[__sval]\n" \
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"1: ldq_l %[__tmp],0(%[__addr64])\n" \
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" extwl %[__tmp],%[__addr16],%[__ret]\n" \
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" mskwl %[__tmp],%[__addr16],%[__tmp]\n" \
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" or %[__sval],%[__tmp],%[__tmp]\n" \
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" stq_c %[__tmp],0(%[__addr64])\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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: [__ret] "=&r" (__ret), \
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[__sval] "=&r" (__sval), \
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[__tmp] "=&r" (__tmp), \
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[__addr64] "=&r" (__addr64) \
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: [__addr16] "r" (mem), \
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[__value] "r" (value) \
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: "memory"); \
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__ret; })
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#define __arch_exchange_32_int(mem, value, mb1, mb2) \
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({ \
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signed int __tmp; __typeof(*mem) __ret; \
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__asm__ __volatile__ ( \
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mb1 \
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"1: ldl_l %[__ret],%[__mem]\n" \
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" mov %[__val],%[__tmp]\n" \
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" stl_c %[__tmp],%[__mem]\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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: [__ret] "=&r" (__ret), \
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[__tmp] "=&r" (__tmp) \
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: [__mem] "m" (*(mem)), \
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[__val] "Ir" (value) \
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: "memory"); \
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__ret; })
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#define __arch_exchange_64_int(mem, value, mb1, mb2) \
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({ \
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unsigned long __tmp; __typeof(*mem) __ret; \
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__asm__ __volatile__ ( \
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mb1 \
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"1: ldq_l %[__ret],%[__mem]\n" \
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" mov %[__val],%[__tmp]\n" \
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" stq_c %[__tmp],%[__mem]\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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: [__ret] "=&r" (__ret), \
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[__tmp] "=&r" (__tmp) \
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: [__mem] "m" (*(mem)), \
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[__val] "Ir" (value) \
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: "memory"); \
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__ret; })
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#define atomic_exchange_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, "", __MB)
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#define atomic_exchange_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __MB, "")
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/* Atomically add value and return the previous (unincremented) value. */
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#define __arch_exchange_and_add_8_int(mem, value, mb1, mb2) \
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({ __builtin_trap (); 0; })
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#define __arch_exchange_and_add_16_int(mem, value, mb1, mb2) \
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({ __builtin_trap (); 0; })
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#define __arch_exchange_and_add_32_int(mem, value, mb1, mb2) \
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({ \
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signed int __tmp; __typeof(*mem) __ret; \
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__asm__ __volatile__ ( \
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mb1 \
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"1: ldl_l %[__ret],%[__mem]\n" \
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" addl %[__ret],%[__val],%[__tmp]\n" \
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" stl_c %[__tmp],%[__mem]\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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: [__ret] "=&r" (__ret), \
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[__tmp] "=&r" (__tmp) \
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: [__mem] "m" (*(mem)), \
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[__val] "Ir" ((signed int)(value)) \
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: "memory"); \
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__ret; })
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#define __arch_exchange_and_add_64_int(mem, value, mb1, mb2) \
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({ \
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unsigned long __tmp; __typeof(*mem) __ret; \
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__asm__ __volatile__ ( \
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mb1 \
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"1: ldq_l %[__ret],%[__mem]\n" \
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" addq %[__ret],%[__val],%[__tmp]\n" \
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" stq_c %[__tmp],%[__mem]\n" \
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" beq %[__tmp],1b\n" \
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mb2 \
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: [__ret] "=&r" (__ret), \
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|
|
[__tmp] "=&r" (__tmp) \
|
||
|
|
: [__mem] "m" (*(mem)), \
|
||
|
|
[__val] "Ir" ((unsigned long)(value)) \
|
||
|
|
: "memory"); \
|
||
|
|
__ret; })
|
||
|
|
|
||
|
|
/* ??? Barrier semantics for atomic_exchange_and_add appear to be
|
||
|
|
undefined. Use full barrier for now, as that's safe. */
|
||
|
|
#define atomic_exchange_and_add(mem, value) \
|
||
|
|
__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, __MB, __MB)
|
||
|
|
|
||
|
|
|
||
|
|
/* ??? Blah, I'm lazy. Implement these later. Can do better than the
|
||
|
|
compare-and-exchange loop provided by generic code.
|
||
|
|
|
||
|
|
#define atomic_decrement_if_positive(mem)
|
||
|
|
#define atomic_bit_test_set(mem, bit)
|
||
|
|
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define atomic_full_barrier() __asm ("mb" : : : "memory");
|
||
|
|
#define atomic_read_barrier() __asm ("mb" : : : "memory");
|
||
|
|
#define atomic_write_barrier() __asm ("wmb" : : : "memory");
|