187 lines
6.5 KiB
Markdown
187 lines
6.5 KiB
Markdown
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;; Scheduling description for GR6.
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;; Copyright (C) 2013-2021 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; GR6 is a dual-issue, superscalar, out-of-order processor.
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;;
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;; The GR6 pipeline has 3 major components:
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;; 1. The FETCH/DECODE/DISPATCH stages, an in-order front-end,
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;; 2. The PROCESS stage, which is the out-of-order core,
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;; 3. The STORE stage, an in-order register storage stage.
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;;
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;; The front-end and the back-end (PROCESS + STORE) are connected through a set
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;; of reservation stations which, among other things, serve as buffers for the
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;; decoded instructions. The reservation stations are attached to a specific
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;; execution unit of the PROCESS stage and the DISPATCH stage is responsible
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;; for dispatching the decoded instructions to the appropriate stations. Most
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;; execution units have multiple reservation stations, thus making it possible
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;; to dispatch two instructions per unit on a given cycle, but only one of them
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;; can be executed on the next cycle.
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;;
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;; Since the core executes the instructions out of order, the most important
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;; consideration for performance tuning is to make sure that enough decoded
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;; instructions are ready for execution in the PROCESS stage while not stalling
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;; the front-end, i.e while not trying to dispatch a decoded instruction to an
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;; execution unit whose reservation stations are full. Therefore, we do not
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;; model the reservation stations (which is equivalent to pretending that there
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;; is only one of them for each execution unit) but only the execution unit,
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;; thus preserving some margin in case the unit itself stalls unexpectedly.
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;; CPU execution units:
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;;
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;; inst[1|2] The front-end: 2 instructions can be issued on a given
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;; cycle by the FETCH/DECODE/DISPATCH stages, except for
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;; the Block Move instructions.
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;;
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;; mov Move Execution Unit: immediate moves into registers.
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;;
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;; alu[1|2] The 2 Arithmetic and Logic Units: other instructions
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;; operating on the registers.
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;;
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;; bru Branch Resolution Unit: all branches.
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;;
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;; mem_wr Memory Write Unit: all writes to memory.
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;;
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;; mem_rd Memory Read Unit: all reads from memory.
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;;
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;; mem_eam EAM interface: reads and writes from and to the EAM
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;; and reads from the FP registers.
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;;
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;; eam Extended Arithmetic Module: multiply, divide and
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;; 64-bit shifts.
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;;
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;; fpcu Floating-Point Compare Unit: FP comparisons.
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;;
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;; fpu[1|2|3|4] The 4 Floating-Point Units: all other instructions
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;; operating on the FP registers.
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(define_automaton "gr6,gr6_fpu")
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(define_cpu_unit "gr6_inst1, gr6_inst2" "gr6")
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(define_cpu_unit "gr6_mov" "gr6")
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(define_cpu_unit "gr6_alu1,gr6_alu2" "gr6")
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(define_cpu_unit "gr6_bru" "gr6")
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(define_cpu_unit "gr6_mem_wr,gr6_mem_rd,gr6_mem_eam" "gr6")
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(define_cpu_unit "gr6_eam" "gr6")
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(define_cpu_unit "gr6_fpcu" "gr6")
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(define_cpu_unit "gr6_fpu1,gr6_fpu2,gr6_fpu3,gr6_fpu4" "gr6_fpu")
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(define_reservation "gr6_issue" "(gr6_inst1 | gr6_inst2)")
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(define_reservation "gr6_single_issue" "gr6_inst1 + gr6_inst2")
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(define_insn_reservation "gr6_immediate" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "imm_reg"))
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"gr6_issue + gr6_mov")
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(define_insn_reservation "gr6_alu" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "arith,arith2,logic,cmp"))
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"gr6_issue + (gr6_alu1 | gr6_alu2)")
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(define_insn_reservation "gr6_branch" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "abs_branch,branch,call,ret,rfi"))
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"gr6_issue + gr6_bru")
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(define_insn_reservation "gr6_block_move" 16
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "bmi"))
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"gr6_single_issue*16")
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(define_insn_reservation "gr6_cpu_other" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "dsi,nop"))
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"gr6_issue")
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(define_insn_reservation "gr6_write_mem" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "reg_mem"))
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"gr6_issue + gr6_mem_wr")
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(define_insn_reservation "gr6_read_mem" 6
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "mem_reg"))
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"gr6_issue + gr6_mem_rd, nothing*5")
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;; EAM instructions.
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(define_insn_reservation "gr6_write_eam" 2
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "reg_eam"))
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"gr6_issue + gr6_mem_eam, nothing")
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(define_reservation "gr6_issue_eam" "gr6_issue + gr6_mem_eam + gr6_eam")
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(define_insn_reservation "gr6_read_eam" 2
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "eam_reg"))
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"gr6_issue_eam, nothing")
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(define_insn_reservation "gr6_shiftdi" 2
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "shiftdi"))
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"gr6_issue_eam, gr6_eam")
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(define_insn_reservation "gr6_mul" 3
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "mul"))
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"gr6_issue_eam, gr6_eam*2")
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(define_insn_reservation "gr6_div" 34
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "div"))
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"gr6_issue_eam, gr6_eam*33")
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(define_insn_reservation "gr6_divd" 66
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "divd"))
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"gr6_issue_eam, gr6_eam*65")
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;; FPU instructions.
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(define_insn_reservation "gr6_read_fp" 2
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "fp_reg"))
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"gr6_issue + gr6_mem_eam, nothing")
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(define_insn_reservation "gr6_cmp_fp" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "fcmp"))
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"gr6_issue + gr6_fpcu")
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(define_insn_reservation "gr6_fp_1cycle" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "fmove,ftoi,itof"))
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"gr6_issue + gr6_fpu1")
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(define_insn_reservation "gr6_fp_3cycle" 3
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "fp"))
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"gr6_issue + gr6_fpu2, nothing*2")
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(define_insn_reservation "gr6_fp_17cycle" 17
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "fdiv,fsqrt"))
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"gr6_issue + gr6_fpu3, gr6_fpu3*14, nothing*2")
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(define_insn_reservation "gr6_write_fp" 1
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(and (eq_attr "cpu" "gr6")
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(eq_attr "type" "reg_fp"))
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"gr6_issue + gr6_fpu4")
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