146 lines
5.0 KiB
Markdown
146 lines
5.0 KiB
Markdown
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;; Scheduling description for GR5.
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;; Copyright (C) 2013-2021 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; GR5 is a single-issue processor.
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;; CPU execution units:
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;;
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;; issue Only one instruction can be issued on a given cycle.
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;; There is no need to model the CPU pipeline in any
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;; more detail than this.
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;;
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;; mem Memory Unit: all accesses to memory.
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;;
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;; eam Extended Arithmetic Module: multiply, divide and
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;; 64-bit shifts.
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;;
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;; fp_slot[0|1|2|3] The 4 FIFO slots of the floating-point unit. Only
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;; the instruction at slot 0 can execute, but an FP
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;; instruction can issue if any of the slots is free.
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(define_automaton "gr5,gr5_fpu")
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(define_cpu_unit "gr5_issue" "gr5")
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(define_cpu_unit "gr5_mem" "gr5")
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(define_cpu_unit "gr5_eam" "gr5")
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(define_cpu_unit "gr5_fp_slot0,gr5_fp_slot1,gr5_fp_slot2,gr5_fp_slot3" "gr5_fpu")
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;; The CPU instructions which write to general registers and so do not totally
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;; complete until they reach the store stage of the pipeline. This is not the
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;; complete storage register class: mem_reg, eam_reg and fpu_reg are excluded
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;; since we must keep the reservation sets non-overlapping.
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(define_insn_reservation "gr5_storage_register" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "imm_reg,arith,arith2,logic,call"))
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"gr5_issue")
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(define_insn_reservation "gr5_read_mem" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "mem_reg"))
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"gr5_issue + gr5_mem")
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;; The latency of 2 and the reservation of gr5_mem on the second cycle ensures
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;; that no reads will be scheduled on the second cycle, which would otherwise
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;; stall the pipeline for 1 cycle.
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(define_insn_reservation "gr5_write_mem" 2
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "reg_mem"))
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"gr5_issue, gr5_mem")
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;; Try to avoid the pipeline hazard of addressing off a register that has
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;; not yet been stored.
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(define_bypass 2 "gr5_storage_register" "gr5_read_mem" "gr5_hazard_bypass_p")
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(define_bypass 2 "gr5_storage_register" "gr5_write_mem" "gr5_hazard_bypass_p")
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(define_bypass 2 "gr5_read_mem" "gr5_read_mem" "gr5_hazard_bypass_p")
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(define_bypass 2 "gr5_read_mem" "gr5_write_mem" "gr5_hazard_bypass_p")
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;; Other CPU instructions complete by the process stage.
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(define_insn_reservation "gr5_cpu_other" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "abs_branch,branch,cmp,ret,rfi,dsi,nop"))
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"gr5_issue")
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;; EAM instructions.
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(define_insn_reservation "gr5_write_eam" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "reg_eam"))
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"gr5_issue")
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(define_reservation "gr5_issue_eam" "(gr5_issue + gr5_eam)")
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(define_insn_reservation "gr5_read_eam" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "eam_reg"))
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"gr5_issue_eam")
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;; Try to avoid the pipeline hazard of addressing off a register that has
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;; not yet been stored.
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(define_bypass 2 "gr5_read_eam" "gr5_read_mem" "gr5_hazard_bypass_p")
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(define_bypass 2 "gr5_read_eam" "gr5_write_mem" "gr5_hazard_bypass_p")
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(define_insn_reservation "gr5_shiftdi" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "shiftdi"))
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"gr5_issue_eam")
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(define_insn_reservation "gr5_mul" 3
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "mul"))
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"gr5_issue_eam, gr5_eam*2")
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(define_insn_reservation "gr5_div" 34
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "div"))
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"gr5_issue_eam, gr5_eam*33")
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(define_insn_reservation "gr5_divd" 66
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "divd"))
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"gr5_issue_eam, gr5_eam*65")
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;; FPU instructions.
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(define_reservation "gr5_fp_slotany" "(gr5_fp_slot0 | gr5_fp_slot1 | gr5_fp_slot2 | gr5_fp_slot3)")
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(define_insn_reservation "gr5_fp_other" 1
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "fp_reg,reg_fp,fcmp"))
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"gr5_issue")
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(define_insn_reservation "gr5_fp_1cycle" 2
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "fmove,ftoi"))
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"gr5_issue + gr5_fp_slotany, gr5_fp_slot0")
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(define_insn_reservation "gr5_fp_2cycle" 3
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "itof"))
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"gr5_issue + gr5_fp_slotany, gr5_fp_slot0*2")
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(define_insn_reservation "gr5_fp_3cycle" 4
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "fp"))
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"gr5_issue + gr5_fp_slotany, gr5_fp_slot0*3")
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(define_insn_reservation "gr5_fp_30cycle" 31
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(and (eq_attr "cpu" "gr5")
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(eq_attr "type" "fdiv,fsqrt"))
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"gr5_issue + gr5_fp_slotany, gr5_fp_slot0*30")
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