243 lines
8.3 KiB
Markdown
243 lines
8.3 KiB
Markdown
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;; Scheduling description for the SPARC M8.
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;; Copyright (C) 2017-2021 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Thigs to improve:
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;;
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;; - Store instructions are implemented by micro-ops, one of which
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;; generates the store address and is executed in the store address
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;; generation unit in the slot0. We need to model that.
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;;
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;; - There are two V3 pipes connected to different slots. The current
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;; implementation assumes that all the instructions executing in a
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;; V3 pipe are issued to the unit in slot3.
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;;
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;; - Single-issue ALU operations incur an additional cycle of latency to
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;; slot 0 and slot 1 instructions. This is not currently reflected
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;; in the DFA.
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(define_automaton "m8_0")
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;; The S5 core has two dual-issue queues, PQLS and PQEX. Each queue
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;; is divided into two slots: PQLS corresponds to slots 0 and 1, and
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;; PQEX corresponds to slots 2 and 3. The core can issue 4
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;; instructions per-cycle, and up to 4 instructions are committed each
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;; cycle.
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;;
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;;
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;; m8_slot0 - Load Unit.
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;; - Store address gen. Unit.
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;;
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;;
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;; === PQLS ==> m8_slot1 - Store data unit.
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;; - Branch unit.
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;;
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;;
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;; === PQEX ==> m8_slot2 - Integer Unit (EXU2).
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;; - 3-cycles Crypto Unit (SPU2).
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;;
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;; m8_slot3 - Integer Unit (EXU3).
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;; - 3-cycles Crypto Unit (SPU3).
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;; - Floating-point and graphics unit (FPG).
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;; - Long-latency Crypto Unit.
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;; - Oracle Numbers Unit (ONU).
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(define_cpu_unit "m8_slot0,m8_slot1,m8_slot2,m8_slot3" "m8_0")
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;; Some instructions stall the pipeline and avoid any other
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;; instruction to be issued in the same cycle. We assume the same for
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;; multi-instruction insns.
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(define_reservation "m8_single_issue" "m8_slot0 + m8_slot1 + m8_slot2 + m8_slot3")
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(define_insn_reservation "m8_single" 1
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "multi,savew,flushw,trap,bmask"))
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"m8_single_issue")
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;; Most of the instructions executing in the integer units have a
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;; latency of 1.
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(define_insn_reservation "m8_integer" 1
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "ialu,ialuX,shift,cmove,compare,bmask"))
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"(m8_slot2 | m8_slot3)")
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;; Flushing the instruction memory takes 27 cycles.
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(define_insn_reservation "m8_iflush" 27
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "iflush"))
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"(m8_slot2 | m8_slot3), nothing*26")
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;; The integer multiplication instructions have a latency of 10 cycles
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;; and execute in integer units.
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;;
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;; Likewise for array*, edge* and pdistn instructions.
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;;
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;; However, the latency is only 9 cycles if the consumer of the
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;; operation is also capable of 9 cycles latency. We model this with
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;; a bypass.
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(define_insn_reservation "m8_imul" 10
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "imul,array,edge,edgen,pdistn"))
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"(m8_slot2 | m8_slot3), nothing*12")
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(define_bypass 9 "m8_imul" "m8_imul")
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;; The integer division instructions `sdiv' and `udivx' have a latency
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;; of 30 cycles and execute in integer units.
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(define_insn_reservation "m8_idiv" 30
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "idiv"))
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"(m8_slot2 | m8_slot3), nothing*29")
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;; Both integer and floating-point load instructions have a latency of
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;; only 3 cycles,and execute in the slot0.
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;;
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;; Misaligned load instructions feature a latency of 11 cycles.
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;;
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;; The prefetch instruction also executes in the load unit, but it's
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;; latency is only 1 cycle.
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(define_insn_reservation "m8_load" 3
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(and (eq_attr "cpu" "m8")
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(ior (eq_attr "type" "fpload,sload")
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(and (eq_attr "type" "load")
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(eq_attr "subtype" "regular"))))
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"m8_slot0, nothing*2")
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;; (define_insn_reservation "m8_load_misalign" 11
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;; (and (eq_attr "cpu" "m8")
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;; (eq_attr "type" "load_mis,fpload_mis"))
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;; "m8_slot0, nothing*10")
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(define_insn_reservation "m8_prefetch" 1
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "load")
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(eq_attr "subtype" "prefetch"))
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"m8_slot0")
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;; Both integer and floating-point store instructions have a latency
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;; of 1 cycle, and execute in the store data unit in slot1.
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;;
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;; However, misaligned store instructions feature a latency of 3
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;; cycles.
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(define_insn_reservation "m8_store" 1
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "store,fpstore"))
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"m8_slot1")
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;; (define_insn_reservation "m8_store_misalign" 3
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;; (and (eq_attr "cpu" "m8")
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;; (eq_attr "type" "store_mis,fpstore_mis"))
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;; "m8_slot1, nothing*2")
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;; Control-transfer instructions execute in the Branch Unit in the
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;; slot1.
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(define_insn_reservation "m8_cti" 1
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
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"m8_slot1")
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;; Many instructions executing in the Floating-point and Graphics Unit
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;; (FGU) serving slot3 feature a default latency of 9 cycles.
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(define_insn_reservation "m8_fp" 9
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(and (eq_attr "cpu" "m8")
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(ior (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul,fgm_pack,fgm_mul,pdist")
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(and (eq_attr "type" "fga")
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(eq_attr "subtype" "fpu"))))
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"m8_slot3, nothing*8")
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;; Floating-point division and floating-point square-root instructions
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;; have high latencies. They execute in the FGU.
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(define_insn_reservation "m8_fpdivs" 26
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "fpdivs"))
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"m8_slot3, nothing*25")
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(define_insn_reservation "m8_fpsqrts" 33
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "fpsqrts"))
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"m8_slot3, nothing*32")
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(define_insn_reservation "m8_fpdivd" 30
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "fpdivd"))
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"m8_slot3, nothing*29")
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(define_insn_reservation "m8_fpsqrtd" 41
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "fpsqrtd"))
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"m8_slot3, nothing*40")
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;; SIMD VIS instructions executing in the Floating-point and graphics
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;; unit (FPG) in slot3 usually have a latency of 5 cycles.
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;;
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;; However, the latency for many instructions is only 3 cycles if the
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;; consumer can also be executed in 3 cycles. We model this with a
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;; bypass. In these cases the instructions are executed in one of the
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;; two 3-cycle crypto units (SPU, also known as "v3-pipes") in slots 2
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;; and 3.
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(define_insn_reservation "m8_vis" 5
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(and (eq_attr "cpu" "m8")
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(ior (eq_attr "type" "viscmp,lzd")
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(and (eq_attr "type" "fga")
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(eq_attr "subtype" "maxmin,cmask,other"))
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(and (eq_attr "type" "vismv")
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(eq_attr "subtype" "single,movstouw"))
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(and (eq_attr "type" "visl")
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(eq_attr "subtype" "single"))))
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"m8_slot3, nothing*4")
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(define_bypass 3 "m8_vis" "m8_vis")
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(define_insn_reservation "m8_gsr" 5
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "gsr")
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(eq_attr "subtype" "alignaddr"))
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"m8_slot3, nothing*4")
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;; A few VIS instructions have a latency of 1.
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(define_insn_reservation "m8_vis_1cycle" 1
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(and (eq_attr "cpu" "m8")
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(ior (and (eq_attr "type" "vismv")
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(eq_attr "subtype" "double,movxtod,movdtox"))
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(and (eq_attr "type" "visl")
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(eq_attr "subtype" "double"))
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(and (eq_attr "type" "fga")
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(eq_attr "subtype" "addsub64"))))
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"m8_slot3")
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;; Reading and writing to the gsr register takes more than 70 cycles.
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(define_insn_reservation "m8_gsr_reg" 70
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(and (eq_attr "cpu" "m8")
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(eq_attr "type" "gsr")
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(eq_attr "subtype" "reg"))
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"m8_slot3, nothing*69")
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