501 lines
15 KiB
Markdown
501 lines
15 KiB
Markdown
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;; Machine description for PowerPC synchronization instructions.
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;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
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;; Contributed by Geoffrey Keating.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_mode_attr larx [(QI "lbarx")
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(HI "lharx")
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(SI "lwarx")
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(DI "ldarx")
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(TI "lqarx")])
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(define_mode_attr stcx [(QI "stbcx.")
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(HI "sthcx.")
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(SI "stwcx.")
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(DI "stdcx.")
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(TI "stqcx.")])
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(define_code_iterator FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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(define_code_attr fetchop_pred
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[(plus "add_operand") (minus "int_reg_operand")
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(ior "logical_operand") (xor "logical_operand") (and "and_operand")])
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(define_expand "mem_thread_fence"
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[(match_operand:SI 0 "const_int_operand")] ;; model
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""
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{
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enum memmodel model = memmodel_base (INTVAL (operands[0]));
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switch (model)
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{
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case MEMMODEL_RELAXED:
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break;
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case MEMMODEL_CONSUME:
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case MEMMODEL_ACQUIRE:
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case MEMMODEL_RELEASE:
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case MEMMODEL_ACQ_REL:
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emit_insn (gen_lwsync ());
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break;
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case MEMMODEL_SEQ_CST:
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emit_insn (gen_hwsync ());
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break;
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default:
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gcc_unreachable ();
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}
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DONE;
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})
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(define_expand "hwsync"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*hwsync"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
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""
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"sync"
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[(set_attr "type" "sync")])
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(define_expand "lwsync"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_LWSYNC))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*lwsync"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_LWSYNC))]
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""
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{
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if (TARGET_NO_LWSYNC)
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return "sync";
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else
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return "lwsync";
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}
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[(set_attr "type" "sync")])
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(define_insn "isync"
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[(unspec_volatile:BLK [(const_int 0)] UNSPECV_ISYNC)]
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""
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"isync"
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[(set_attr "type" "isync")])
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;; Types that we should provide atomic instructions for.
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(define_mode_iterator AINT [QI
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HI
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SI
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(DI "TARGET_POWERPC64")
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(TI "TARGET_SYNC_TI")])
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;; The control dependency used for load dependency described
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;; in B.2.3 of the Power ISA 2.06B.
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(define_insn "loadsync_<mode>"
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[(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]
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UNSPECV_ISYNC)
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(clobber (match_scratch:CC 1 "=y"))]
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""
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"cmpw %1,%0,%0\;bne- %1,$+4\;isync"
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[(set_attr "type" "isync")
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(set_attr "length" "12")])
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;; If TARGET_PREFIXED, always use plq rather than lq.
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(define_insn "load_quadpti"
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[(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
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(unspec:PTI
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[(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]
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"TARGET_SYNC_TI
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&& !reg_mentioned_p (operands[0], operands[1])"
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"lq %0,%1"
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[(set_attr "type" "load")
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(set_attr "size" "128")
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(set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED")
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(const_string "yes")
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(const_string "no")))])
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;; Pattern load_quadpti will always use plq for atomic TImode if
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;; TARGET_PREFIXED. It has the correct doubleword ordering on either LE
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;; or BE, so we can just move the result into the output register and
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;; do not need to do the doubleword swap for LE. Also this avoids any
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;; confusion about whether the lq vs plq might be used based on whether
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;; op1 has PC-relative addressing. We could potentially allow BE to
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;; use lq because it doesn't have the doubleword ordering problem.
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(define_expand "atomic_load<mode>"
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[(set (match_operand:AINT 0 "register_operand") ;; output
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(match_operand:AINT 1 "memory_operand")) ;; memory
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(use (match_operand:SI 2 "const_int_operand"))] ;; model
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""
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{
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if (<MODE>mode == TImode && !TARGET_SYNC_TI)
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FAIL;
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enum memmodel model = memmodel_base (INTVAL (operands[2]));
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if (is_mm_seq_cst (model))
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emit_insn (gen_hwsync ());
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if (<MODE>mode != TImode)
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emit_move_insn (operands[0], operands[1]);
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else
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{
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rtx op0 = operands[0];
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rtx op1 = operands[1];
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rtx pti_reg = gen_reg_rtx (PTImode);
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if (!quad_address_p (XEXP (op1, 0), TImode, false))
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{
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rtx old_addr = XEXP (op1, 0);
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rtx new_addr = force_reg (Pmode, old_addr);
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operands[1] = op1 = replace_equiv_address (op1, new_addr);
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}
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emit_insn (gen_load_quadpti (pti_reg, op1));
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if (WORDS_BIG_ENDIAN || TARGET_PREFIXED)
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emit_move_insn (op0, gen_lowpart (TImode, pti_reg));
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else
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{
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emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg));
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emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg));
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}
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}
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switch (model)
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{
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case MEMMODEL_RELAXED:
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break;
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case MEMMODEL_CONSUME:
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case MEMMODEL_ACQUIRE:
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case MEMMODEL_SEQ_CST:
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emit_insn (gen_loadsync_<mode> (operands[0]));
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break;
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default:
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gcc_unreachable ();
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}
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DONE;
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})
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;; If TARGET_PREFIXED, always use pstq rather than stq.
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(define_insn "store_quadpti"
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[(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")
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(unspec:PTI
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[(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
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"TARGET_SYNC_TI"
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"stq %1,%0"
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[(set_attr "type" "store")
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(set_attr "size" "128")
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(set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED")
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(const_string "yes")
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(const_string "no")))])
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;; Pattern store_quadpti will always use pstq if TARGET_PREFIXED,
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;; so the doubleword swap is never needed in that case.
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(define_expand "atomic_store<mode>"
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[(set (match_operand:AINT 0 "memory_operand") ;; memory
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(match_operand:AINT 1 "register_operand")) ;; input
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(use (match_operand:SI 2 "const_int_operand"))] ;; model
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""
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{
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if (<MODE>mode == TImode && !TARGET_SYNC_TI)
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FAIL;
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enum memmodel model = memmodel_base (INTVAL (operands[2]));
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switch (model)
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{
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case MEMMODEL_RELAXED:
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break;
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case MEMMODEL_RELEASE:
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emit_insn (gen_lwsync ());
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break;
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case MEMMODEL_SEQ_CST:
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emit_insn (gen_hwsync ());
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break;
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default:
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gcc_unreachable ();
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}
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if (<MODE>mode != TImode)
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emit_move_insn (operands[0], operands[1]);
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else
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{
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rtx op0 = operands[0];
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rtx op1 = operands[1];
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rtx pti_reg = gen_reg_rtx (PTImode);
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if (!quad_address_p (XEXP (op0, 0), TImode, false))
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{
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rtx old_addr = XEXP (op0, 0);
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rtx new_addr = force_reg (Pmode, old_addr);
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operands[0] = op0 = replace_equiv_address (op0, new_addr);
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}
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if (WORDS_BIG_ENDIAN || TARGET_PREFIXED)
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emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));
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else
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{
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emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1));
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emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1));
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}
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emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));
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}
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DONE;
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})
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;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons
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;; other than the quad memory operations, which have special restrictions.
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;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased
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;; in and did not show up until power8. TImode atomic lqarx/stqcx. require
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;; special handling due to even/odd register requirements.
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(define_mode_iterator ATOMIC [(QI "TARGET_SYNC_HI_QI")
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(HI "TARGET_SYNC_HI_QI")
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SI
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(DI "TARGET_POWERPC64")])
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(define_insn "load_locked<mode>"
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[(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
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(unspec_volatile:ATOMIC
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[(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]
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""
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"<larx> %0,%y1"
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[(set_attr "type" "load_l")])
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(define_insn "load_locked<QHI:mode>_si"
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[(set (match_operand:SI 0 "int_reg_operand" "=r")
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(unspec_volatile:SI
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[(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]
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"TARGET_SYNC_HI_QI"
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"<QHI:larx> %0,%y1"
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[(set_attr "type" "load_l")])
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;; Use PTImode to get even/odd register pairs.
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;; Use a temporary register to force getting an even register for the
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;; lqarx/stqcrx. instructions. Normal optimizations will eliminate this extra
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;; copy on big endian systems.
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;; On little endian systems where non-atomic quad word load/store instructions
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;; are not used, the address can be register+offset, so make sure the address
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;; is indexed or indirect before register allocation.
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(define_expand "load_lockedti"
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[(use (match_operand:TI 0 "quad_int_reg_operand"))
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(use (match_operand:TI 1 "memory_operand"))]
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"TARGET_SYNC_TI"
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{
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rtx op0 = operands[0];
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rtx op1 = operands[1];
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rtx pti = gen_reg_rtx (PTImode);
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if (!indexed_or_indirect_operand (op1, TImode))
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{
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rtx old_addr = XEXP (op1, 0);
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rtx new_addr = force_reg (Pmode, old_addr);
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operands[1] = op1 = change_address (op1, TImode, new_addr);
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}
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emit_insn (gen_load_lockedpti (pti, op1));
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if (WORDS_BIG_ENDIAN)
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emit_move_insn (op0, gen_lowpart (TImode, pti));
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else
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{
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emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti));
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emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti));
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}
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DONE;
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})
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(define_insn "load_lockedpti"
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[(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
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(unspec_volatile:PTI
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[(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]
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"TARGET_SYNC_TI
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&& !reg_mentioned_p (operands[0], operands[1])
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&& quad_int_reg_operand (operands[0], PTImode)"
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"lqarx %0,%y1"
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[(set_attr "type" "load_l")
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(set_attr "size" "128")])
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(define_insn "store_conditional<mode>"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
|
||
|
|
(set (match_operand:ATOMIC 1 "memory_operand" "=Z")
|
||
|
|
(match_operand:ATOMIC 2 "int_reg_operand" "r"))]
|
||
|
|
""
|
||
|
|
"<stcx> %2,%y1"
|
||
|
|
[(set_attr "type" "store_c")])
|
||
|
|
|
||
|
|
;; Use a temporary register to force getting an even register for the
|
||
|
|
;; lqarx/stqcrx. instructions. Normal optimizations will eliminate this extra
|
||
|
|
;; copy on big endian systems.
|
||
|
|
|
||
|
|
;; On little endian systems where non-atomic quad word load/store instructions
|
||
|
|
;; are not used, the address can be register+offset, so make sure the address
|
||
|
|
;; is indexed or indirect before register allocation.
|
||
|
|
|
||
|
|
(define_expand "store_conditionalti"
|
||
|
|
[(use (match_operand:CC 0 "cc_reg_operand"))
|
||
|
|
(use (match_operand:TI 1 "memory_operand"))
|
||
|
|
(use (match_operand:TI 2 "quad_int_reg_operand"))]
|
||
|
|
"TARGET_SYNC_TI"
|
||
|
|
{
|
||
|
|
rtx op0 = operands[0];
|
||
|
|
rtx op1 = operands[1];
|
||
|
|
rtx op2 = operands[2];
|
||
|
|
rtx addr = XEXP (op1, 0);
|
||
|
|
rtx pti_mem;
|
||
|
|
rtx pti_reg;
|
||
|
|
|
||
|
|
if (!indexed_or_indirect_operand (op1, TImode))
|
||
|
|
{
|
||
|
|
rtx new_addr = force_reg (Pmode, addr);
|
||
|
|
operands[1] = op1 = change_address (op1, TImode, new_addr);
|
||
|
|
addr = new_addr;
|
||
|
|
}
|
||
|
|
|
||
|
|
pti_mem = change_address (op1, PTImode, addr);
|
||
|
|
pti_reg = gen_reg_rtx (PTImode);
|
||
|
|
|
||
|
|
if (WORDS_BIG_ENDIAN)
|
||
|
|
emit_move_insn (pti_reg, gen_lowpart (PTImode, op2));
|
||
|
|
else
|
||
|
|
{
|
||
|
|
emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op2));
|
||
|
|
emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op2));
|
||
|
|
}
|
||
|
|
|
||
|
|
emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg));
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_insn "store_conditionalpti"
|
||
|
|
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
||
|
|
(unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
|
||
|
|
(set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z")
|
||
|
|
(match_operand:PTI 2 "quad_int_reg_operand" "r"))]
|
||
|
|
"TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"
|
||
|
|
"stqcx. %2,%y1"
|
||
|
|
[(set_attr "type" "store_c")
|
||
|
|
(set_attr "size" "128")])
|
||
|
|
|
||
|
|
(define_expand "atomic_compare_and_swap<mode>"
|
||
|
|
[(match_operand:SI 0 "int_reg_operand") ;; bool out
|
||
|
|
(match_operand:AINT 1 "int_reg_operand") ;; val out
|
||
|
|
(match_operand:AINT 2 "memory_operand") ;; memory
|
||
|
|
(match_operand:AINT 3 "reg_or_short_operand") ;; expected
|
||
|
|
(match_operand:AINT 4 "int_reg_operand") ;; desired
|
||
|
|
(match_operand:SI 5 "const_int_operand") ;; is_weak
|
||
|
|
(match_operand:SI 6 "const_int_operand") ;; model succ
|
||
|
|
(match_operand:SI 7 "const_int_operand")] ;; model fail
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_compare_and_swap (operands);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_exchange<mode>"
|
||
|
|
[(match_operand:AINT 0 "int_reg_operand") ;; output
|
||
|
|
(match_operand:AINT 1 "memory_operand") ;; memory
|
||
|
|
(match_operand:AINT 2 "int_reg_operand") ;; input
|
||
|
|
(match_operand:SI 3 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_exchange (operands);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_<fetchop_name><mode>"
|
||
|
|
[(match_operand:AINT 0 "memory_operand") ;; memory
|
||
|
|
(FETCHOP:AINT (match_dup 0)
|
||
|
|
(match_operand:AINT 1 "<fetchop_pred>")) ;; operand
|
||
|
|
(match_operand:SI 2 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_op (<CODE>, operands[0], operands[1],
|
||
|
|
NULL_RTX, NULL_RTX, operands[2]);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_nand<mode>"
|
||
|
|
[(match_operand:AINT 0 "memory_operand") ;; memory
|
||
|
|
(match_operand:AINT 1 "int_reg_operand") ;; operand
|
||
|
|
(match_operand:SI 2 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_op (NOT, operands[0], operands[1],
|
||
|
|
NULL_RTX, NULL_RTX, operands[2]);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_fetch_<fetchop_name><mode>"
|
||
|
|
[(match_operand:AINT 0 "int_reg_operand") ;; output
|
||
|
|
(match_operand:AINT 1 "memory_operand") ;; memory
|
||
|
|
(FETCHOP:AINT (match_dup 1)
|
||
|
|
(match_operand:AINT 2 "<fetchop_pred>")) ;; operand
|
||
|
|
(match_operand:SI 3 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
|
||
|
|
operands[0], NULL_RTX, operands[3]);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_fetch_nand<mode>"
|
||
|
|
[(match_operand:AINT 0 "int_reg_operand") ;; output
|
||
|
|
(match_operand:AINT 1 "memory_operand") ;; memory
|
||
|
|
(match_operand:AINT 2 "int_reg_operand") ;; operand
|
||
|
|
(match_operand:SI 3 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
|
||
|
|
operands[0], NULL_RTX, operands[3]);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_<fetchop_name>_fetch<mode>"
|
||
|
|
[(match_operand:AINT 0 "int_reg_operand") ;; output
|
||
|
|
(match_operand:AINT 1 "memory_operand") ;; memory
|
||
|
|
(FETCHOP:AINT (match_dup 1)
|
||
|
|
(match_operand:AINT 2 "<fetchop_pred>")) ;; operand
|
||
|
|
(match_operand:SI 3 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
|
||
|
|
NULL_RTX, operands[0], operands[3]);
|
||
|
|
DONE;
|
||
|
|
})
|
||
|
|
|
||
|
|
(define_expand "atomic_nand_fetch<mode>"
|
||
|
|
[(match_operand:AINT 0 "int_reg_operand") ;; output
|
||
|
|
(match_operand:AINT 1 "memory_operand") ;; memory
|
||
|
|
(match_operand:AINT 2 "int_reg_operand") ;; operand
|
||
|
|
(match_operand:SI 3 "const_int_operand")] ;; model
|
||
|
|
""
|
||
|
|
{
|
||
|
|
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
|
||
|
|
NULL_RTX, operands[0], operands[3]);
|
||
|
|
DONE;
|
||
|
|
})
|