402 lines
13 KiB
Markdown
402 lines
13 KiB
Markdown
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;; Machine description for the PCREL_OPT optimization.
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;; Copyright (C) 2020-2021 Free Software Foundation, Inc.
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;; Contributed by Michael Meissner (meissner@linux.ibm.com)
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Support for the PCREL_OPT optimization. PCREL_OPT looks for instances where
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;; an external variable is used only once, either for reading or for writing.
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;;
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;; If we are optimizing a single read, normally the code would look like:
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;;
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;; (set (reg:DI <ptr>)
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;; (symbol_ref:DI "<extern_addr>")) # <data> is currently dead
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;;
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;; ... # insns do not need to be adjacent
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;;
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;; (set (reg:SI <data>)
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;; (mem:SI (reg:DI <xxx>))) # <ptr> dies with this insn
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;;
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;; We transform this into:
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;;
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;; (parallel [(set (reg:DI <ptr>)
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;; (unspec:SI [(symbol_ref:DI <extern_addr>)
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;; (const_int <marker>)]
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;; UNSPEC_PCREL_OPT_LD_ADDR))
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;; (set (reg:DI <data>)
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;; (unspec:DI [(const_int 0)]
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;; UNSPEC_PCREL_OPT_LD_DATA))])
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;;
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;; ...
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;;
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;; (parallel [(set (reg:SI <data>)
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;; (unspec:SI [(mem:SI (reg:DI <ptr>))
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;; (reg:DI <data>)
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;; (const_int <marker>)]
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;; UNSPEC_PCREL_OPT_LD_RELOC))
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;; (clobber (reg:DI <ptr>))])
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;;
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;; The marker is an integer constant that links the load of the external
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;; address to the load of the actual variable.
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;;
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;; In the first insn, we set both the address of the external variable, and
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;; mark that the variable being loaded both are created in that insn, and are
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;; consumed in the second insn. It doesn't matter what mode the register that
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;; we will ultimately do the load into, so we use DImode. We just need to mark
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;; that both registers may be set in the first insn, and will be used in the
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;; second insn.
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;;
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;; Since we use UNSPEC's and link both the the register holding the external
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;; address and the value being loaded, it should prevent other passes from
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;; modifying it.
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;;
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;; If the register being loaded is the same as the base register, we use an
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;; alternate form of the insns.
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;;
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;; (set (reg:DI <data_ptr>)
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;; (unspec:DI [(symbol_ref:DI <extern_addr>)
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;; (const_int <marker>)]
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;; UNSPEC_PCREL_OPT_LD_SAME_REG))
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;;
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;; ...
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;;
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;; (parallel [(set (reg:SI <data>)
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;; (unspec:SI [(mem:SI (reg:DI <ptr>))
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;; (reg:DI <data>)
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;; (const_int <marker>)]
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;; UNSPEC_PCREL_OPT_LD_RELOC))
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;; (clobber (reg:DI <ptr>))])
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(define_c_enum "unspec"
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[UNSPEC_PCREL_OPT_LD_ADDR
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UNSPEC_PCREL_OPT_LD_DATA
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UNSPEC_PCREL_OPT_LD_SAME_REG
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UNSPEC_PCREL_OPT_LD_RELOC
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UNSPEC_PCREL_OPT_ST_ADDR
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UNSPEC_PCREL_OPT_ST_RELOC])
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;; Modes that are supported for PCREL_OPT
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(define_mode_iterator PCRELOPT [QI HI SI DI TI SF DF KF
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V1TI V2DI V4SI V8HI V16QI V2DF V4SF
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(TF "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD")])
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;; Vector modes for PCREL_OPT
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(define_mode_iterator PCRELOPT_VECT [TI KF V1TI V2DI V4SI V8HI V16QI V2DF V4SF
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(TF "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD")])
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;; Insn for loading the external address, where the register being loaded is not
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;; the same as the register being loaded with the data.
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(define_insn "pcrel_opt_ld_addr"
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[(set (match_operand:DI 0 "base_reg_operand" "=&b,&b")
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(unspec:DI [(match_operand:DI 1 "pcrel_external_address")
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(match_operand 2 "const_int_operand" "n,n")]
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UNSPEC_PCREL_OPT_LD_ADDR))
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(set (match_operand:DI 3 "gpc_reg_operand" "=r,wa")
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(unspec:DI [(const_int 0)]
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UNSPEC_PCREL_OPT_LD_DATA))]
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"TARGET_PCREL_OPT
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&& reg_or_subregno (operands[0]) != reg_or_subregno (operands[3])"
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"ld %0,%a1\n.Lpcrel%2:"
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[(set_attr "prefixed" "yes")
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(set_attr "type" "load")
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(set_attr "loads_external_address" "yes")])
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;; Alternate form of loading up the external address that is the same register
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;; as the final load.
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(define_insn "pcrel_opt_ld_addr_same_reg"
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[(set (match_operand:DI 0 "base_reg_operand" "=b")
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(unspec:DI [(match_operand:DI 1 "pcrel_external_address")
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(match_operand 2 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_LD_SAME_REG))]
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"TARGET_PCREL_OPT"
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"ld %0,%a1\n.Lpcrel%2:"
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[(set_attr "prefixed" "yes")
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(set_attr "type" "load")
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(set_attr "loads_external_address" "yes")])
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;; PCREL_OPT modes that are optimized for loading or storing GPRs.
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(define_mode_iterator PCRELOPT_GPR [QI HI SI DI SF DF])
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(define_mode_attr PCRELOPT_GPR_LD [(QI "lbz")
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(HI "lhz")
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(SI "lwz")
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(SF "lwz")
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(DI "ld")
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(DF "ld")])
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;; PCREL_OPT load operation of GPRs. Operand 4 (the register used to hold the
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;; address of the external symbol) is SCRATCH if the same register is used for
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;; the normal load.
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(define_insn "*pcrel_opt_ld<mode>_gpr"
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[(parallel [(set (match_operand:PCRELOPT_GPR 0 "int_reg_operand" "+r")
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(unspec:PCRELOPT_GPR [
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(match_operand:PCRELOPT_GPR 1 "d_form_memory" "m")
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(match_operand:DI 2 "int_reg_operand" "0")
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(match_operand 3 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_LD_RELOC))
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(clobber (match_scratch:DI 4 "=bX"))])]
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"TARGET_PCREL_OPT
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&& (GET_CODE (operands[4]) == SCRATCH
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|| reg_mentioned_p (operands[4], operands[1]))"
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{
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output_pcrel_opt_reloc (operands[3]);
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return "<PCRELOPT_GPR_LD> %0,%1";
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}
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[(set_attr "type" "load")])
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;; PCREL_OPT load with sign/zero extension
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(define_insn "*pcrel_opt_ldsi_<u><mode>_gpr"
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[(set (match_operand:EXTSI 0 "int_reg_operand" "+r")
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(any_extend:EXTSI
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(unspec:SI [(match_operand:SI 1 "d_form_memory" "m")
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(match_operand:DI 2 "int_reg_operand" "0")
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(match_operand 3 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_LD_RELOC)))
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(clobber (match_scratch:DI 4 "=bX"))]
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"TARGET_PCREL_OPT"
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{
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output_pcrel_opt_reloc (operands[3]);
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return "lw<az> %0,%1";
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}
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[(set_attr "type" "load")])
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(define_insn "*pcrel_opt_ldhi_<u><mode>_gpr"
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[(set (match_operand:EXTHI 0 "int_reg_operand" "+r")
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(any_extend:EXTHI
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(unspec:HI [(match_operand:HI 1 "d_form_memory" "m")
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(match_operand:DI 2 "int_reg_operand" "0")
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(match_operand 3 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_LD_RELOC)))
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(clobber (match_scratch:DI 4 "=bX"))]
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"TARGET_PCREL_OPT"
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{
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output_pcrel_opt_reloc (operands[3]);
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return "lh<az> %0,%1";
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}
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[(set_attr "type" "load")])
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(define_insn "*pcrel_opt_ldqi_u<mode>_gpr"
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[(set (match_operand:EXTQI 0 "int_reg_operand" "+r")
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(zero_extend:EXTQI
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(unspec:QI [(match_operand:QI 1 "d_form_memory" "m")
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(match_operand:DI 2 "int_reg_operand" "0")
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(match_operand 3 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_LD_RELOC)))
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(clobber (match_scratch:DI 4 "=bX"))]
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"TARGET_PCREL_OPT"
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{
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output_pcrel_opt_reloc (operands[3]);
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return "lbz %0,%1";
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}
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[(set_attr "type" "load")])
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;; Scalar types that can be optimized by loading them into floating point
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;; or Altivec registers.
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(define_mode_iterator PCRELOPT_FP [DI DF SF])
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;; Load instructions to load up scalar floating point or 64-bit integer values
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;; into floating point registers or Altivec registers.
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(define_mode_attr PCRELOPT_FPR_LD [(DI "lfd") (DF "lfd") (SF "lfs")])
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(define_mode_attr PCRELOPT_VMX_LD [(DI "lxsd") (DF "lxsd") (SF "lxssp")])
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;; PCREL_OPT load operation of scalar DF/DI/SF into vector registers.
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(define_insn "*pcrel_opt_ld<mode>_vsx"
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[(set (match_operand:PCRELOPT_FP 0 "vsx_register_operand" "+d,v")
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(unspec:PCRELOPT_FP [(match_operand:PCRELOPT_FP 1 "d_form_memory" "m,m")
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(match_operand:DI 2 "vsx_register_operand" "0,0")
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(match_operand 3 "const_int_operand" "n,n")]
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UNSPEC_PCREL_OPT_LD_RELOC))
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(clobber (match_operand:DI 4 "base_reg_operand" "=b,b"))]
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"TARGET_PCREL_OPT"
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{
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output_pcrel_opt_reloc (operands[3]);
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return which_alternative ? "<PCRELOPT_VMX_LD> %0,%1"
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: "<PCRELOPT_FPR_LD> %0,%1";
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}
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[(set_attr "type" "fpload")])
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;; PCREL_OPT optimization extending SFmode to DFmode via a load.
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(define_insn "*pcrel_opt_ldsf_df"
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[(set (match_operand:DF 0 "vsx_register_operand" "+d,v")
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(float_extend:DF
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(unspec:SF [(match_operand:SF 1 "d_form_memory" "m,m")
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(match_operand:DI 2 "vsx_register_operand" "0,0")
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(match_operand 3 "const_int_operand" "n,n")]
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UNSPEC_PCREL_OPT_LD_RELOC)))
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(clobber (match_operand:DI 4 "base_reg_operand" "=b,b"))]
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"TARGET_PCREL_OPT"
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{
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output_pcrel_opt_reloc (operands[3]);
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return which_alternative ? "lxssp %0,%1" : "lfs %0,%1";
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}
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[(set_attr "type" "fpload")])
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;; PCREL_OPT load operation of vector/float128 types into vector registers.
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(define_insn "*pcrel_opt_ld<mode>"
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[(set (match_operand:PCRELOPT_VECT 0 "vsx_register_operand" "+wa")
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(unspec:PCRELOPT_VECT [(match_operand:PCRELOPT_VECT 1 "d_form_memory" "m")
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(match_operand:DI 2 "vsx_register_operand" "0")
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(match_operand 3 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_LD_RELOC))
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(clobber (match_operand:DI 4 "base_reg_operand" "=b"))]
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"TARGET_PCREL_OPT"
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{
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output_pcrel_opt_reloc (operands[3]);
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return "lxv %x0,%1";
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}
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[(set_attr "type" "vecload")])
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;; PCREL_OPT optimization for stores. We need to put the label after the PLD
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;; instruction, because the assembler might insert a NOP before the PLD for
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;; alignment.
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;;
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;; If we are optimizing a single write, normally the code would look like:
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;;
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;; (set (reg:DI <ptr>)
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;; (symbol_ref:DI "<extern_addr>")) # <data> must be live here
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;;
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;; ... # insns do not need to be adjacent
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;;
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;; (set (mem:SI (reg:DI <xxx>))
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;; (reg:SI <data>)) # <ptr> dies with this insn
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;;
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;; We optimize this to be:
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;;
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;; (parallel [(set (reg:DI <ptr>)
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;; (unspec:DI [(symbol_ref:DI "<extern_addr>")
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;; (const_int <marker>)]
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;; UNSPEC_PCREL_OPT_ST_ADDR))
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;; (use (reg:<MODE> <data>))])
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;;
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;; ... # insns do not need to be adjacent
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;;
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;; (parallel [(set (mem:<MODE> (reg:DI <ptr>))
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;; (unspec:<MODE> [(reg:<MODE> <data>)
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;; (const_int <marker>)]
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;; UNSPEC_PCREL_OPT_ST_RELOC))
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;; (clobber (reg:DI <ptr>))])
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(define_insn "*pcrel_opt_st_addr<mode>"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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(unspec:DI [(match_operand:DI 1 "pcrel_external_address")
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(match_operand 2 "const_int_operand" "n")]
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UNSPEC_PCREL_OPT_ST_ADDR))
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(use (match_operand:PCRELOPT 3 "gpc_reg_operand" "rwa"))]
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"TARGET_PCREL_OPT"
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"ld %0,%a1\n.Lpcrel%2:"
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|||
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|
[(set_attr "prefixed" "yes")
|
|||
|
|
(set_attr "type" "load")
|
|||
|
|
(set_attr "loads_external_address" "yes")])
|
|||
|
|
|
|||
|
|
;; PCREL_OPT stores.
|
|||
|
|
(define_insn "*pcrel_opt_st<mode>"
|
|||
|
|
[(set (match_operand:QHSI 0 "d_form_memory" "=m")
|
|||
|
|
(unspec:QHSI [(match_operand:QHSI 1 "gpc_reg_operand" "r")
|
|||
|
|
(match_operand 2 "const_int_operand" "n")]
|
|||
|
|
UNSPEC_PCREL_OPT_ST_RELOC))
|
|||
|
|
(clobber (match_operand:DI 3 "base_reg_operand" "=b"))]
|
|||
|
|
"TARGET_PCREL_OPT"
|
|||
|
|
{
|
|||
|
|
output_pcrel_opt_reloc (operands[2]);
|
|||
|
|
return "st<wd> %1,%0";
|
|||
|
|
}
|
|||
|
|
[(set_attr "type" "store")])
|
|||
|
|
|
|||
|
|
(define_insn "*pcrel_opt_stdi"
|
|||
|
|
[(set (match_operand:DI 0 "d_form_memory" "=m,m,m")
|
|||
|
|
(unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "r,d,v")
|
|||
|
|
(match_operand 2 "const_int_operand" "n,n,n")]
|
|||
|
|
UNSPEC_PCREL_OPT_ST_RELOC))
|
|||
|
|
(clobber (match_operand:DI 3 "base_reg_operand" "=b,b,b"))]
|
|||
|
|
"TARGET_PCREL_OPT && TARGET_POWERPC64"
|
|||
|
|
{
|
|||
|
|
output_pcrel_opt_reloc (operands[2]);
|
|||
|
|
switch (which_alternative)
|
|||
|
|
{
|
|||
|
|
case 0:
|
|||
|
|
return "std %1,%0";
|
|||
|
|
case 1:
|
|||
|
|
return "stfd %1,%0";
|
|||
|
|
case 2:
|
|||
|
|
return "stxsd %1,%0";
|
|||
|
|
default:
|
|||
|
|
gcc_unreachable ();
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
[(set_attr "type" "store,fpstore,fpstore")])
|
|||
|
|
|
|||
|
|
(define_insn "*pcrel_opt_stsf"
|
|||
|
|
[(set (match_operand:SF 0 "d_form_memory" "=m,m,m")
|
|||
|
|
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "d,v,r")
|
|||
|
|
(match_operand 2 "const_int_operand" "n,n,n")]
|
|||
|
|
UNSPEC_PCREL_OPT_ST_RELOC))
|
|||
|
|
(clobber (match_operand:DI 3 "base_reg_operand" "=b,b,b"))]
|
|||
|
|
"TARGET_PCREL_OPT"
|
|||
|
|
{
|
|||
|
|
output_pcrel_opt_reloc (operands[2]);
|
|||
|
|
switch (which_alternative)
|
|||
|
|
{
|
|||
|
|
case 0:
|
|||
|
|
return "stfs %1,%0";
|
|||
|
|
case 1:
|
|||
|
|
return "stxssp %1,%0";
|
|||
|
|
case 2:
|
|||
|
|
return "stw %1,%0";
|
|||
|
|
default:
|
|||
|
|
gcc_unreachable ();
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
[(set_attr "type" "fpstore,fpstore,store")])
|
|||
|
|
|
|||
|
|
(define_insn "*pcrel_opt_stdf"
|
|||
|
|
[(set (match_operand:DF 0 "d_form_memory" "=m,m,m")
|
|||
|
|
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d,v,r")
|
|||
|
|
(match_operand 2 "const_int_operand" "n,n,n")]
|
|||
|
|
UNSPEC_PCREL_OPT_ST_RELOC))
|
|||
|
|
(clobber (match_operand:DI 3 "base_reg_operand" "=b,b,b"))]
|
|||
|
|
"TARGET_PCREL_OPT
|
|||
|
|
&& (TARGET_POWERPC64 || vsx_register_operand (operands[1], DFmode))"
|
|||
|
|
{
|
|||
|
|
output_pcrel_opt_reloc (operands[2]);
|
|||
|
|
switch (which_alternative)
|
|||
|
|
{
|
|||
|
|
case 0:
|
|||
|
|
return "stfd %1,%0";
|
|||
|
|
case 1:
|
|||
|
|
return "stxsd %1,%0";
|
|||
|
|
case 2:
|
|||
|
|
return "std %1,%0";
|
|||
|
|
default:
|
|||
|
|
gcc_unreachable ();
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
[(set_attr "type" "fpstore,fpstore,store")])
|
|||
|
|
|
|||
|
|
(define_insn "*pcrel_opt_st<mode>"
|
|||
|
|
[(set (match_operand:PCRELOPT_VECT 0 "d_form_memory" "=m")
|
|||
|
|
(unspec:PCRELOPT_VECT [(match_operand:PCRELOPT_VECT 1 "gpc_reg_operand" "wa")
|
|||
|
|
(match_operand 2 "const_int_operand" "n")]
|
|||
|
|
UNSPEC_PCREL_OPT_ST_RELOC))
|
|||
|
|
(clobber (match_operand:DI 3 "base_reg_operand" "=b"))]
|
|||
|
|
"TARGET_PCREL_OPT"
|
|||
|
|
{
|
|||
|
|
output_pcrel_opt_reloc (operands[2]);
|
|||
|
|
return "stxv %x1,%0";
|
|||
|
|
}
|
|||
|
|
[(set_attr "type" "vecstore")])
|