229 lines
6.7 KiB
Markdown
229 lines
6.7 KiB
Markdown
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;; Pipeline description for Freescale PowerPC e6500 core.
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;; Copyright (C) 2012-2021 Free Software Foundation, Inc.
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;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
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;; Max issue 3 insns/clock cycle (includes 1 branch)
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(define_automaton "e6500_most,e6500_long,e6500_vec")
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(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
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;; SFX.
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(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
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;; CFX.
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(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
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;; Non-pipelined division.
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(define_cpu_unit "e6500_cfx_div" "e6500_long")
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;; LSU.
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(define_cpu_unit "e6500_lsu" "e6500_most")
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;; FPU.
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(define_cpu_unit "e6500_fpu" "e6500_long")
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;; BU.
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(define_cpu_unit "e6500_bu" "e6500_most")
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;; Altivec unit
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(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
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;; The following units are used to make the automata deterministic.
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(define_cpu_unit "present_e6500_decode_0" "e6500_most")
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(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
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(presence_set "present_e6500_decode_0" "e6500_decode_0")
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(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
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;; Some useful abbreviations.
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(define_reservation "e6500_decode"
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"e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
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(define_reservation "e6500_sfx"
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"e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
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;; SFX.
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(define_insn_reservation "e6500_sfx" 1
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(and (ior (eq_attr "type" "integer,insert,cntlz")
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(and (eq_attr "type" "add,logical,exts")
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(eq_attr "dot" "no"))
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(and (eq_attr "type" "shift")
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(eq_attr "dot" "no")
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(eq_attr "var_shift" "no")))
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx")
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(define_insn_reservation "e6500_sfx2" 2
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(and (ior (eq_attr "type" "cmp,trap")
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(and (eq_attr "type" "add,logical,exts")
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(eq_attr "dot" "yes"))
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(and (eq_attr "type" "shift")
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(eq_attr "dot" "yes")
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(eq_attr "var_shift" "no")))
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx")
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(define_insn_reservation "e6500_delayed" 2
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(and (eq_attr "type" "shift")
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(eq_attr "var_shift" "yes")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx*2")
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(define_insn_reservation "e6500_two" 2
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
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(define_insn_reservation "e6500_three" 3
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
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;; SFX - Mfcr.
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(define_insn_reservation "e6500_mfcr" 4
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx_0*4")
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;; SFX - Mtcrf.
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(define_insn_reservation "e6500_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx_0")
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;; SFX - Mtjmpr.
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(define_insn_reservation "e6500_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx")
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;; CFX - Multiply.
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(define_insn_reservation "e6500_multiply" 4
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(and (eq_attr "type" "mul")
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(eq_attr "dot" "no")
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(eq_attr "size" "32")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
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(define_insn_reservation "e6500_multiply_i" 5
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(and (eq_attr "type" "mul")
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(ior (eq_attr "dot" "yes")
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(eq_attr "size" "8,16"))
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_cfx_stage0,\
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e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
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;; CFX - Divide.
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(define_insn_reservation "e6500_divide" 16
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(and (eq_attr "type" "div")
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(eq_attr "size" "32")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
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e6500_cfx_div*15")
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(define_insn_reservation "e6500_divide_d" 26
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(and (eq_attr "type" "div")
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(eq_attr "size" "64")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
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e6500_cfx_div*25")
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;; LSU - Loads.
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(define_insn_reservation "e6500_load" 3
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(and (eq_attr "type" "load,load_l,sync")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_lsu")
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(define_insn_reservation "e6500_fpload" 4
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_lsu")
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(define_insn_reservation "e6500_vecload" 4
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(and (eq_attr "type" "vecload")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_lsu")
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;; LSU - Stores.
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(define_insn_reservation "e6500_store" 3
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(and (eq_attr "type" "store,store_c")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_lsu")
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(define_insn_reservation "e6500_fpstore" 3
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_lsu")
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(define_insn_reservation "e6500_vecstore" 4
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_lsu")
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;; FP.
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(define_insn_reservation "e6500_float" 7
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(and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_fpu")
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(define_insn_reservation "e6500_sdiv" 20
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_fpu*20")
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(define_insn_reservation "e6500_ddiv" 35
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_fpu*35")
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;; BU.
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(define_insn_reservation "e6500_branch" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_bu")
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;; BU - CR logical.
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(define_insn_reservation "e6500_cr_logical" 1
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(and (eq_attr "type" "cr_logical")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_bu")
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;; VSFX.
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(define_insn_reservation "e6500_vecsimple" 1
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(and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_vec")
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;; VCFX.
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(define_insn_reservation "e6500_veccomplex" 4
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(and (eq_attr "type" "veccomplex")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_vec")
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;; VFPU.
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(define_insn_reservation "e6500_vecfloat" 6
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(and (eq_attr "type" "vecfloat")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_vec")
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;; VPERM.
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(define_insn_reservation "e6500_vecperm" 2
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(and (eq_attr "type" "vecperm")
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_vecperm")
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