193 lines
6.8 KiB
Markdown
193 lines
6.8 KiB
Markdown
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;; Pipeline description for Motorola PowerPC e500mc core.
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;; Copyright (C) 2008-2021 Free Software Foundation, Inc.
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;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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;; e500mc 32-bit SU(2), LSU, FPU, BPU
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;; Max issue 3 insns/clock cycle (includes 1 branch)
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;; FP is half clocked, timings of other instructions are as in the e500v2.
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(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
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(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
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(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
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(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
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;; SU.
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(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
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;; MU.
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(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
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(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
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;; Non-pipelined division.
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(define_cpu_unit "e500mc_mu_div" "e500mc_long")
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;; LSU.
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(define_cpu_unit "e500mc_lsu" "e500mc_most")
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;; FPU.
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(define_cpu_unit "e500mc_fpu" "e500mc_most")
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;; Branch unit.
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(define_cpu_unit "e500mc_bu" "e500mc_most")
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;; The following units are used to make the automata deterministic.
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(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
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(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
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(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
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(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
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;; The following sets to make automata deterministic when option ndfa is used.
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(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
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(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
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(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
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(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
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;; Some useful abbreviations.
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(define_reservation "e500mc_decode"
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"e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
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(define_reservation "e500mc_issue"
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"e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
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(define_reservation "e500mc_retire"
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"e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
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(define_reservation "e500mc_su_stage0"
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"e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
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;; Simple SU insns.
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(define_insn_reservation "e500mc_su" 1
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(and (eq_attr "type" "integer,add,logical,insert,cmp,\
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shift,trap,cntlz,exts,isel")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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(define_insn_reservation "e500mc_two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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e500mc_issue+e500mc_su_stage0+e500mc_retire")
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(define_insn_reservation "e500mc_three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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e500mc_issue+e500mc_su_stage0+e500mc_retire")
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;; Multiply.
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(define_insn_reservation "e500mc_multiply" 4
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(and (eq_attr "type" "mul")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
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e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
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;; Divide. We use the average latency time here.
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(define_insn_reservation "e500mc_divide" 14
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(and (eq_attr "type" "div")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
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e500mc_mu_div*13")
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;; Branch.
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(define_insn_reservation "e500mc_branch" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_bu,e500mc_retire")
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;; CR logical.
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(define_insn_reservation "e500mc_cr_logical" 1
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(and (eq_attr "type" "cr_logical")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_bu,e500mc_retire")
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;; Mfcr.
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(define_insn_reservation "e500mc_mfcr" 1
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
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;; Mtcrf.
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(define_insn_reservation "e500mc_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
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;; Mtjmpr.
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(define_insn_reservation "e500mc_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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;; Loads.
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(define_insn_reservation "e500mc_load" 3
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(and (eq_attr "type" "load,load_l,sync")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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(define_insn_reservation "e500mc_fpload" 4
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
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;; Stores.
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(define_insn_reservation "e500mc_store" 3
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(and (eq_attr "type" "store,store_c")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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(define_insn_reservation "e500mc_fpstore" 3
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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;; The following ignores the retire unit to avoid a large automata.
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;; Simple FP.
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(define_insn_reservation "e500mc_simple_float" 8
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(and (eq_attr "type" "fpsimple")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
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;; FP.
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(define_insn_reservation "e500mc_float" 8
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
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(define_insn_reservation "e500mc_fpcompare" 8
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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(define_insn_reservation "e500mc_dmul" 10
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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;; FP divides are not pipelined.
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(define_insn_reservation "e500mc_sdiv" 36
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
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(define_insn_reservation "e500mc_ddiv" 66
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
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