246 lines
7.7 KiB
Markdown
246 lines
7.7 KiB
Markdown
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/* Machine description patterns for PowerPC running Darwin (Mac OS X).
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Copyright (C) 2004-2021 Free Software Foundation, Inc.
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Contributed by Apple Computer Inc.
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This file is part of GCC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>. */
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(define_insn "adddi3_high"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(high:DI (match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_64BIT"
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"addis %0,%1,ha16(%2)")
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(define_insn "movdf_low_si"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
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{
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switch (which_alternative)
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{
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case 0:
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return "lfd %0,lo16(%2)(%1)";
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case 1:
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{
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if (TARGET_POWERPC64 && TARGET_32BIT)
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/* Note, old assemblers didn't support relocation here. */
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return "ld %0,lo16(%2)(%1)";
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else
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{
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output_asm_insn ("la %0,lo16(%2)(%1)", operands);
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output_asm_insn ("lwz %L0,4(%0)", operands);
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return ("lwz %0,0(%0)");
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}
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "load")
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(set_attr "length" "4,12")])
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(define_insn "movdf_low_di"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
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"@
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lfd %0,lo16(%2)(%1)
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ld %0,lo16(%2)(%1)"
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[(set_attr "type" "load")])
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(define_insn "movdf_low_st_si"
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[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
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"stfd %0,lo16(%2)(%1)"
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[(set_attr "type" "store")])
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(define_insn "movdf_low_st_di"
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[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
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"stfd %0,lo16(%2)(%1)"
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[(set_attr "type" "store")])
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(define_insn "movsf_low_si"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
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"@
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lfs %0,lo16(%2)(%1)
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lwz %0,lo16(%2)(%1)"
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[(set_attr "type" "load")])
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(define_insn "movsf_low_di"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
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"@
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lfs %0,lo16(%2)(%1)
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lwz %0,lo16(%2)(%1)"
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[(set_attr "type" "load")])
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(define_insn "movsf_low_st_si"
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[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" "")))
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
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"@
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stfs %0,lo16(%2)(%1)
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stw %0,lo16(%2)(%1)"
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[(set_attr "type" "store")])
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(define_insn "movsf_low_st_di"
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[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" "")))
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
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"@
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stfs %0,lo16(%2)(%1)
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stw %0,lo16(%2)(%1)"
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[(set_attr "type" "store")])
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;; Mach-O PIC.
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(define_insn "@macho_high_<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
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(high:P (match_operand 1 "" "")))]
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"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && !flag_pic"
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"lis %0,ha16(%1)")
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(define_insn "@macho_low_<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=r")
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(lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))]
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"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && !flag_pic"
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"la %0,lo16(%2)(%1)")
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(define_insn "@machopic_high_<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
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(high:P (match_operand 1 "macho_pic_address" "")))]
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"TARGET_MACHO && flag_pic"
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"lis %0,ha16(%1)")
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(define_insn "@machopic_low_<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=r")
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(lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
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(match_operand 2 "macho_pic_address" "")))]
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"TARGET_MACHO && flag_pic"
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"la %0,lo16(%2)(%1)")
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(define_split
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[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
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(match_operand:DI 1 "short_cint_operand")))
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(match_operand:V4SI 2 "register_operand"))
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(clobber (match_operand:DI 3 "gpc_reg_operand"))]
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"TARGET_MACHO && TARGET_64BIT"
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[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
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(set (mem:V4SI (match_dup 3))
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(match_dup 2))]
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"")
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(define_insn "@macho_correct_pic_<mode>"
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[(set (match_operand:P 0 "gpc_reg_operand" "=r")
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(plus:P (match_operand:P 1 "gpc_reg_operand" "r")
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(unspec:P [(match_operand:P 2 "immediate_operand" "s")
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(match_operand:P 3 "immediate_operand" "s")]
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UNSPEC_MPIC_CORRECT)))]
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"DEFAULT_ABI == ABI_DARWIN"
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"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
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[(set_attr "length" "8")])
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(define_insn "@load_macho_picbase_<mode>"
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[(set (reg:P LR_REGNO)
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(unspec:P [(match_operand:P 0 "immediate_operand" "s")
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(pc)] UNSPEC_LD_MPIC))]
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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{
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#if TARGET_MACHO
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machopic_should_output_picbase_label (); /* Update for new func. */
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#else
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gcc_unreachable ();
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#endif
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return "bcl 20,31,%0\n%0:";
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}
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[(set_attr "type" "branch")
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(set_attr "cannot_copy" "yes")])
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(define_insn "@reload_macho_picbase_<mode>"
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[(set (reg:P LR_REGNO)
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(unspec:P [(match_operand:P 0 "immediate_operand" "s")
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(pc)] UNSPEC_RELD_MPIC))]
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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{
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#if TARGET_MACHO
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if (machopic_should_output_picbase_label ())
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{
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static char tmp[64];
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const char *cnam = machopic_get_function_picbase ();
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snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
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return tmp;
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}
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else
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#else
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gcc_unreachable ();
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#endif
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return "bcl 20,31,%0\n%0:";
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}
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[(set_attr "type" "branch")
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(set_attr "cannot_copy" "yes")])
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;; We need to restore the PIC register, at the site of nonlocal label.
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(define_insn_and_split "nonlocal_goto_receiver"
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[(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
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"TARGET_MACHO && flag_pic"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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#if TARGET_MACHO
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if (crtl->uses_pic_offset_table)
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{
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static unsigned n = 0;
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rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
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rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
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rtx tmplrtx;
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char tmplab[20];
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ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
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tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
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emit_insn (gen_reload_macho_picbase (Pmode, tmplrtx));
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emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
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emit_insn (gen_macho_correct_pic (Pmode, picreg, picreg,
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picrtx, tmplrtx));
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}
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else
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/* Not using PIC reg, no reload needed. */
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emit_note (NOTE_INSN_DELETED);
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#else
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gcc_unreachable ();
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#endif
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DONE;
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})
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