233 lines
7.4 KiB
Markdown
233 lines
7.4 KiB
Markdown
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;; ALU operations with zero extensions
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;;
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;; Copyright (C) 2015-2021 Free Software Foundation, Inc.
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;; Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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; All PRU ALU instructions automatically zero-extend their source operands,
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; and zero-extract the result into the destination register. This is
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; described in the machine description by defining a separate pattern
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; for each possible combination of zero_extend and mode for input operands.
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;
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; An unfortunate side effect is that quite a few invalid RTL patterns are
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; generated. For example:
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; ... (zero_extend:SI (match_operand:SI ...)) ...
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; These patterns are harmless since no pass should generate such RTL. This
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; shortcut allows us to keep small and concise machine description patterns.
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(define_subst_attr "alu2_zext" "alu2_zext_subst" "_z" "_noz")
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(define_subst_attr "alu3_zext_op1" "alu3_zext_op1_subst" "_z1" "_noz1")
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(define_subst_attr "alu3_zext_op2" "alu3_zext_op2_subst" "_z2" "_noz2")
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(define_subst_attr "alu3_zext" "alu3_zext_subst" "_z" "_noz")
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(define_subst_attr "lmbd_zext_op1" "lmbd_zext_op1_subst" "_z1" "_noz1")
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(define_subst_attr "lmbd_zext_op2" "lmbd_zext_op2_subst" "_z2" "_noz2")
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(define_subst_attr "lmbd_zext" "lmbd_zext_subst" "_z" "_noz")
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(define_subst_attr "bitalu_zext" "bitalu_zext_subst" "_z" "_noz")
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(define_code_iterator ALUOP3 [plus minus and ior xor umin umax ashift lshiftrt])
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(define_code_iterator ALUOP2 [neg not])
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;; Arithmetic Operations
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(define_insn "add_impl<EQD:mode><EQS0:mode><EQS1:mode>_<alu3_zext><alu3_zext_op1><alu3_zext_op2>"
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[(set (match_operand:EQD 0 "register_operand" "=r,r,r")
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(plus:EQD
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(zero_extend:EQD
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(match_operand:EQS0 1 "register_operand" "%r,r,r"))
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(zero_extend:EQD
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(match_operand:EQS1 2 "nonmemory_operand" "r,<EQS1:ubyte_constr>,M"))))]
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""
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"@
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add\\t%0, %1, %2
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add\\t%0, %1, %u2
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sub\\t%0, %1, %n2"
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[(set_attr "type" "alu")])
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(define_insn "sub_impl<EQD:mode><EQS0:mode><EQS1:mode>_<alu3_zext><alu3_zext_op1><alu3_zext_op2>"
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[(set (match_operand:EQD 0 "register_operand" "=r,r")
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(minus:EQD
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(zero_extend:EQD
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(match_operand:EQS0 1 "reg_or_ubyte_operand" "r,<EQS0:ubyte_constr>"))
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(zero_extend:EQD
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(match_operand:EQS1 2 "register_operand" "r,r"))))]
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""
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"@
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sub\\t%0, %1, %2
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rsb\\t%0, %2, %u1"
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[(set_attr "type" "alu")])
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;; Left Most Bit Detect instruction.
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(define_insn "pru_lmbd_impl<EQD:mode><EQS0:mode><EQS1:mode>_<lmbd_zext><lmbd_zext_op1><lmbd_zext_op2>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(unspec:EQD
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[(zero_extend:EQD
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(match_operand:EQS0 1 "register_operand" "r"))
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(zero_extend:EQD
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(match_operand:EQS1 2 "reg_or_ubyte_operand" "r<EQS1:ubyte_constr>"))]
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UNSPEC_LMBD))]
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""
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"lmbd\t%0, %1, %2"
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[(set_attr "type" "alu")])
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(define_insn "neg_impl<EQD:mode><EQS0:mode>_<alu2_zext>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(neg:EQD
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(zero_extend:EQD (match_operand:EQS0 1 "register_operand" "r"))))]
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""
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"rsb\\t%0, %1, 0"
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[(set_attr "type" "alu")])
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(define_insn "one_cmpl_impl<EQD:mode><EQS0:mode>_<alu2_zext>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(not:EQD
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(zero_extend:EQD (match_operand:EQS0 1 "register_operand" "r"))))]
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""
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"not\\t%0, %1"
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[(set_attr "type" "alu")])
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; Specialized IOR/AND patterns for matching setbit/clearbit instructions.
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;
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; TODO - allow clrbit and setbit to support (1 << REG) constructs
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(define_insn "clearbit_<EQD:mode><EQS0:mode>_<bitalu_zext>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(and:EQD
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(zero_extend:EQD
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(match_operand:EQS0 1 "register_operand" "r"))
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(match_operand:EQD 2 "single_zero_operand" "n")))]
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""
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"clr\\t%0, %1, %V2"
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[(set_attr "type" "alu")])
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(define_insn "setbit_<EQD:mode><EQS0:mode>_<bitalu_zext>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(ior:EQD
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(zero_extend:EQD
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(match_operand:EQS0 1 "register_operand" "r"))
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(match_operand:EQD 2 "single_one_operand" "n")))]
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""
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"set\\t%0, %1, %T2"
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[(set_attr "type" "alu")])
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; Regular ALU ops
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(define_insn "<code>_impl<EQD:mode><EQS0:mode><EQS1:mode>_<alu3_zext><alu3_zext_op1><alu3_zext_op2>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(LOGICAL:EQD
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(zero_extend:EQD
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(match_operand:EQS0 1 "register_operand" "%r"))
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(zero_extend:EQD
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(match_operand:EQS1 2 "reg_or_ubyte_operand" "r<EQS1:ubyte_constr>"))))]
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""
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"<logical_asm>\\t%0, %1, %u2"
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[(set_attr "type" "alu")])
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; Shift ALU ops
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(define_insn "<shift_op>_impl<EQD:mode><EQS0:mode><EQS1:mode>_<alu3_zext><alu3_zext_op1><alu3_zext_op2>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(SHIFT:EQD
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(zero_extend:EQD (match_operand:EQS0 1 "register_operand" "r"))
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(zero_extend:EQD (match_operand:EQS1 2 "shift_operand" "rL"))))]
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""
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"<shift_asm>\\t%0, %1, %2"
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[(set_attr "type" "alu")])
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;; Substitutions
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(define_subst "alu2_zext_subst"
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[(set (match_operand:EQD 0)
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(ALUOP2:EQD (zero_extend:EQD (match_operand:EQD 1))))]
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""
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[(set (match_dup 0)
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(ALUOP2:EQD (match_dup 1)))])
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(define_subst "bitalu_zext_subst"
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[(set (match_operand:EQD 0)
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(ALUOP3:EQD (zero_extend:EQD (match_operand:EQD 1))
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(match_operand:EQD 2)))]
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""
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[(set (match_dup 0)
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(ALUOP3:EQD (match_dup 1)
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(match_dup 2)))])
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(define_subst "alu3_zext_subst"
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[(set (match_operand:EQD 0)
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(ALUOP3:EQD (zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQD 2))))]
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""
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[(set (match_dup 0)
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(ALUOP3:EQD (match_dup 1)
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(match_dup 2)))])
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(define_subst "alu3_zext_op1_subst"
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[(set (match_operand:EQD 0)
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(ALUOP3:EQD (zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQS1 2))))]
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""
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[(set (match_dup 0)
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(ALUOP3:EQD (match_dup 1)
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(zero_extend:EQD (match_dup 2))))])
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(define_subst "alu3_zext_op2_subst"
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[(set (match_operand:EQD 0)
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(ALUOP3:EQD (zero_extend:EQD (match_operand:EQS0 1))
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(zero_extend:EQD (match_operand:EQD 2))))]
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""
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[(set (match_dup 0)
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(ALUOP3:EQD (zero_extend:EQD (match_dup 1))
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(match_dup 2)))])
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(define_subst "lmbd_zext_subst"
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[(set (match_operand:EQD 0)
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(unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQD 2))]
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UNSPEC_LMBD))]
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""
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[(set (match_dup 0)
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(unspec:EQD [(match_dup 1)
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(match_dup 2)]
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UNSPEC_LMBD))])
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(define_subst "lmbd_zext_op1_subst"
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[(set (match_operand:EQD 0)
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(unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQS1 2))]
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UNSPEC_LMBD))]
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""
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[(set (match_dup 0)
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(unspec:EQD [(match_dup 1)
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(zero_extend:EQD (match_dup 2))]
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UNSPEC_LMBD))])
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(define_subst "lmbd_zext_op2_subst"
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[(set (match_operand:EQD 0)
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(unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQD 2))]
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UNSPEC_LMBD))]
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""
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[(set (match_dup 0)
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(unspec:EQD [(zero_extend:EQD (match_dup 1))
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(match_dup 2)]
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UNSPEC_LMBD))])
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