466 lines
12 KiB
Plaintext
466 lines
12 KiB
Plaintext
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; Options of Andes NDS32 cpu for GNU compiler
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; Copyright (C) 2012-2021 Free Software Foundation, Inc.
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; Contributed by Andes Technology Corporation.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it
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; under the terms of the GNU General Public License as published
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; by the Free Software Foundation; either version 3, or (at your
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; option) any later version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; <http://www.gnu.org/licenses/>.
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HeaderInclude
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config/nds32/nds32-opts.h
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; ---------------------------------------------------------------
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; The following options are designed for aliasing and compatibility options.
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EB
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Target RejectNegative Alias(mbig-endian)
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Generate code in big-endian mode.
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EL
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Target RejectNegative Alias(mlittle-endian)
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Generate code in little-endian mode.
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mfp-as-gp
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Target RejectNegative Alias(mforce-fp-as-gp)
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Force performing fp-as-gp optimization.
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mno-fp-as-gp
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Target RejectNegative Alias(mforbid-fp-as-gp)
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Forbid performing fp-as-gp optimization.
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; ---------------------------------------------------------------
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mabi=
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Target RejectNegative Joined Enum(abi_type) Var(nds32_abi) Init(TARGET_DEFAULT_ABI)
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Specify which ABI type to generate code for: 2, 2fp+.
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Enum
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Name(abi_type) Type(enum abi_type)
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Known ABIs (for use with the -mabi= option):
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EnumValue
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Enum(abi_type) String(2) Value(NDS32_ABI_V2)
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EnumValue
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Enum(abi_type) String(2fp+) Value(NDS32_ABI_V2_FP_PLUS)
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mfloat-abi=soft
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Target RejectNegative Alias(mabi=, 2)
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Specify use soft floating point ABI which mean alias to -mabi=2.
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mfloat-abi=hard
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Target RejectNegative Alias(mabi=, 2fp+)
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Specify use soft floating point ABI which mean alias to -mabi=2fp+.
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; ---------------------------------------------------------------
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mreduced-regs
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Target RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
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Use reduced-set registers for register allocation.
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mfull-regs
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Target RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
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Use full-set registers for register allocation.
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; ---------------------------------------------------------------
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malways-align
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Target Mask(ALWAYS_ALIGN)
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Always align function entry, jump target and return address.
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malign-functions
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Target Mask(ALIGN_FUNCTION)
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Align function entry to 4 byte.
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mbig-endian
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Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
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Generate code in big-endian mode.
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mlittle-endian
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Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
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Generate code in little-endian mode.
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mforce-fp-as-gp
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Target Undocumented Mask(FORCE_FP_AS_GP)
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Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.
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mforbid-fp-as-gp
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Target Undocumented Mask(FORBID_FP_AS_GP)
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Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.
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mict-model=
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Target Undocumented RejectNegative Joined Enum(nds32_ict_model_type) Var(nds32_ict_model) Init(ICT_MODEL_SMALL)
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Specify the address generation strategy for ICT call's code model.
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Enum
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Name(nds32_ict_model_type) Type(enum nds32_ict_model_type)
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Known cmodel types (for use with the -mict-model= option):
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EnumValue
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Enum(nds32_ict_model_type) String(small) Value(ICT_MODEL_SMALL)
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EnumValue
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Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE)
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mcmov
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Target Mask(CMOV)
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Generate conditional move instructions.
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mhw-abs
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Target Mask(HW_ABS)
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Generate hardware abs instructions.
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mext-perf
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Target Mask(EXT_PERF)
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Generate performance extension instructions.
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mext-perf2
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Target Mask(EXT_PERF2)
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Generate performance extension version 2 instructions.
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mext-string
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Target Mask(EXT_STRING)
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Generate string extension instructions.
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mext-dsp
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Target Mask(EXT_DSP)
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Generate DSP extension instructions.
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mv3push
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Target Mask(V3PUSH)
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Generate v3 push25/pop25 instructions.
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m16-bit
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Target Mask(16_BIT)
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Generate 16-bit instructions.
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mrelax-hint
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Target Mask(RELAX_HINT)
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Insert relax hint for linker to do relaxation.
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mvh
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Target Mask(VH) Condition(!TARGET_LINUX_ABI)
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Enable Virtual Hosting support.
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misr-vector-size=
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Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
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Specify the size of each interrupt vector, which must be 4 or 16.
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misr-secure=
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Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0)
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Specify the security level of c-isr for the whole file.
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mcache-block-size=
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Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
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Specify the size of each cache block, which must be a power of 2 between 4 and 512.
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march=
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Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
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Specify the name of the target architecture.
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Enum
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Name(nds32_arch_type) Type(enum nds32_arch_type)
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Known arch types (for use with the -march= option):
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EnumValue
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Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
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EnumValue
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Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
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EnumValue
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Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J)
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EnumValue
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Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
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EnumValue
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Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F)
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EnumValue
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Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S)
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mcpu=
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Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9)
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Specify the cpu for pipeline model.
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Enum
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Name(nds32_cpu_type) Type(enum nds32_cpu_type)
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Known cpu types (for use with the -mcpu= option):
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EnumValue
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Enum(nds32_cpu_type) String(n6) Value(CPU_N6)
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EnumValue
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Enum(nds32_cpu_type) String(n650) Value(CPU_N6)
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EnumValue
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Enum(nds32_cpu_type) String(n7) Value(CPU_N7)
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EnumValue
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Enum(nds32_cpu_type) String(n705) Value(CPU_N7)
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EnumValue
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Enum(nds32_cpu_type) String(n8) Value(CPU_N8)
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EnumValue
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Enum(nds32_cpu_type) String(n801) Value(CPU_N8)
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EnumValue
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Enum(nds32_cpu_type) String(sn8) Value(CPU_N8)
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EnumValue
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Enum(nds32_cpu_type) String(sn801) Value(CPU_N8)
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EnumValue
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Enum(nds32_cpu_type) String(s8) Value(CPU_N8)
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EnumValue
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Enum(nds32_cpu_type) String(s801) Value(CPU_N8)
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EnumValue
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Enum(nds32_cpu_type) String(e8) Value(CPU_E8)
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EnumValue
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Enum(nds32_cpu_type) String(e801) Value(CPU_E8)
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EnumValue
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Enum(nds32_cpu_type) String(n820) Value(CPU_E8)
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EnumValue
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Enum(nds32_cpu_type) String(s830) Value(CPU_E8)
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EnumValue
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Enum(nds32_cpu_type) String(e830) Value(CPU_E8)
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EnumValue
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Enum(nds32_cpu_type) String(n9) Value(CPU_N9)
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EnumValue
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Enum(nds32_cpu_type) String(n903) Value(CPU_N9)
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EnumValue
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Enum(nds32_cpu_type) String(n903a) Value(CPU_N9)
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EnumValue
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Enum(nds32_cpu_type) String(n968) Value(CPU_N9)
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EnumValue
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Enum(nds32_cpu_type) String(n968a) Value(CPU_N9)
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EnumValue
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Enum(nds32_cpu_type) String(n10) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1033) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1068) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(d10) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(d1088) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10)
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EnumValue
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Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF)
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EnumValue
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Enum(nds32_cpu_type) String(n12) Value(CPU_N12)
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EnumValue
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Enum(nds32_cpu_type) String(n1213) Value(CPU_N12)
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EnumValue
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Enum(nds32_cpu_type) String(n1233) Value(CPU_N12)
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EnumValue
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Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12)
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EnumValue
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Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12)
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EnumValue
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Enum(nds32_cpu_type) String(n13) Value(CPU_N13)
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EnumValue
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Enum(nds32_cpu_type) String(n1337) Value(CPU_N13)
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EnumValue
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Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13)
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EnumValue
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Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13)
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EnumValue
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Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE)
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mconfig-fpu=
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Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT)
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Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3.
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Enum
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Name(float_reg_number) Type(enum float_reg_number)
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Known floating-point number of registers (for use with the -mconfig-fpu= option):
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EnumValue
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Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0)
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EnumValue
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Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1)
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EnumValue
|
||
|
|
Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7)
|
||
|
|
|
||
|
|
mconfig-mul=
|
||
|
|
Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1)
|
||
|
|
Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1.
|
||
|
|
|
||
|
|
Enum
|
||
|
|
Name(nds32_mul_type) Type(enum nds32_mul_type)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(nds32_mul_type) String(fast) Value(MUL_TYPE_FAST_1)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW)
|
||
|
|
|
||
|
|
mconfig-register-ports=
|
||
|
|
Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W)
|
||
|
|
Specify how many read/write ports for n9/n10 cores. The value should be 3r2w or 2r1w.
|
||
|
|
|
||
|
|
Enum
|
||
|
|
Name(nds32_register_ports) Type(enum nds32_register_ports)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W)
|
||
|
|
|
||
|
|
EnumValue
|
||
|
|
Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
|
||
|
|
|
||
|
|
mctor-dtor
|
||
|
|
Target
|
||
|
|
Enable constructor/destructor feature.
|
||
|
|
|
||
|
|
mrelax
|
||
|
|
Target
|
||
|
|
Guide linker to relax instructions.
|
||
|
|
|
||
|
|
mext-fpu-fma
|
||
|
|
Target Mask(EXT_FPU_FMA)
|
||
|
|
Generate floating-point multiply-accumulation instructions.
|
||
|
|
|
||
|
|
mext-fpu-sp
|
||
|
|
Target Mask(FPU_SINGLE)
|
||
|
|
Generate single-precision floating-point instructions.
|
||
|
|
|
||
|
|
mext-fpu-dp
|
||
|
|
Target Mask(FPU_DOUBLE)
|
||
|
|
Generate double-precision floating-point instructions.
|
||
|
|
|
||
|
|
mforce-no-ext-dsp
|
||
|
|
Target Undocumented Mask(FORCE_NO_EXT_DSP)
|
||
|
|
Force disable hardware loop, even use -mext-dsp.
|
||
|
|
|
||
|
|
msched-prolog-epilog
|
||
|
|
Target Var(flag_sched_prolog_epilog) Init(0)
|
||
|
|
Permit scheduling of a function's prologue and epilogue sequence.
|
||
|
|
|
||
|
|
mret-in-naked-func
|
||
|
|
Target Var(flag_ret_in_naked_func) Init(1)
|
||
|
|
Generate return instruction in naked function.
|
||
|
|
|
||
|
|
malways-save-lp
|
||
|
|
Target Var(flag_always_save_lp) Init(0)
|
||
|
|
Always save $lp in the stack.
|
||
|
|
|
||
|
|
munaligned-access
|
||
|
|
Target Var(flag_unaligned_access) Init(0)
|
||
|
|
Enable unaligned word and halfword accesses to packed data.
|
||
|
|
|
||
|
|
minline-asm-r15
|
||
|
|
Target Var(flag_inline_asm_r15) Init(0)
|
||
|
|
Allow use r15 for inline ASM.
|