358 lines
17 KiB
Markdown
358 lines
17 KiB
Markdown
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;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
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;; Copyright (C) 2012-2021 Free Software Foundation, Inc.
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;; Contributed by Andes Technology Corporation.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; ------------------------------------------------------------------------
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;; Define N9 3R2W pipeline settings.
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;; ------------------------------------------------------------------------
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(define_automaton "nds32_n9_3r2w_machine")
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;; ------------------------------------------------------------------------
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;; Pipeline Stages
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;; ------------------------------------------------------------------------
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;; IF - Instruction Fetch
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;; II - Instruction Issue / Instruction Decode
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;; EX - Instruction Execution
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;; MM - Memory Execution
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;; WB - Instruction Retire / Result Write-Back
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(define_cpu_unit "n9_3r2w_ii" "nds32_n9_3r2w_machine")
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(define_cpu_unit "n9_3r2w_ex" "nds32_n9_3r2w_machine")
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(define_cpu_unit "n9_3r2w_mm" "nds32_n9_3r2w_machine")
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(define_cpu_unit "n9_3r2w_wb" "nds32_n9_3r2w_machine")
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(define_insn_reservation "nds_n9_3r2w_unknown" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "unknown")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_misc" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "misc")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_mmu" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "mmu")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_alu" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "alu")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_alu_shift" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "alu_shift")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_pbsad" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "pbsad")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex*3, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_pbsada" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "type" "pbsada")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex*3, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (match_test "nds32::load_single_p (insn)")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (match_test "nds32::store_single_p (insn)")
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(eq_attr "pipeline_model" "n9")))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_1" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "1"))))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_2" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(ior (and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "2"))
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(match_test "nds32::load_double_p (insn)"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_3" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "3"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_4" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "4"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_5" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "5"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*2, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_6" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "6"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*3, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_7" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "7"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*4, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_8" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "8"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*5, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_load_multiple_12" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "load_multiple")
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(eq_attr "combo" "12"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*9, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_1" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "1"))))
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"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_2" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(ior (and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "2"))
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(match_test "nds32::store_double_p (insn)"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_3" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "3"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_4" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "4"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_5" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "5"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*2, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_6" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "6"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*3, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_7" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
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(and (eq_attr "type" "store_multiple")
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(eq_attr "combo" "7"))))
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"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*4, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
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(define_insn_reservation "nds_n9_3r2w_store_multiple_8" 1
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(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
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(and (eq_attr "pipeline_model" "n9")
|
||
|
|
(and (eq_attr "type" "store_multiple")
|
||
|
|
(eq_attr "combo" "8"))))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*5, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_store_multiple_12" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
|
||
|
|
(and (eq_attr "pipeline_model" "n9")
|
||
|
|
(and (eq_attr "type" "store_multiple")
|
||
|
|
(eq_attr "combo" "12"))))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*9, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_mul_fast1" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_1")
|
||
|
|
(and (eq_attr "type" "mul")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_mul_fast2" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_2")
|
||
|
|
(and (eq_attr "type" "mul")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex*2, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_mul_slow" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_SLOW")
|
||
|
|
(and (eq_attr "type" "mul")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex*17, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_mac_fast1" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_1")
|
||
|
|
(and (eq_attr "type" "mac")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_mac_fast2" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_2")
|
||
|
|
(and (eq_attr "type" "mac")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex*2, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_mac_slow" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_SLOW")
|
||
|
|
(and (eq_attr "type" "mac")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex*17, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_div" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
|
||
|
|
(and (eq_attr "type" "div")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex*34, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
(define_insn_reservation "nds_n9_3r2w_branch" 1
|
||
|
|
(and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
|
||
|
|
(and (eq_attr "type" "branch")
|
||
|
|
(eq_attr "pipeline_model" "n9")))
|
||
|
|
"n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
|
||
|
|
|
||
|
|
;; ------------------------------------------------------------------------
|
||
|
|
;; Comment Notations and Bypass Rules
|
||
|
|
;; ------------------------------------------------------------------------
|
||
|
|
;; Producers (LHS)
|
||
|
|
;; LD
|
||
|
|
;; Load data from the memory and produce the loaded data. The result is
|
||
|
|
;; ready at MM.
|
||
|
|
;; LMW(N, M)
|
||
|
|
;; There are N micro-operations within an instruction that loads multiple
|
||
|
|
;; words. The result produced by the M-th micro-operation is sent to
|
||
|
|
;; consumers. The result is ready at MM.
|
||
|
|
;; MUL, MAC
|
||
|
|
;; Compute data in the multiply-adder and produce the data. The result
|
||
|
|
;; is ready at MM.
|
||
|
|
;; DIV
|
||
|
|
;; Compute data in the divider and produce the data. The result is ready
|
||
|
|
;; at MM.
|
||
|
|
;;
|
||
|
|
;; Consumers (RHS)
|
||
|
|
;; ALU, MOVD44, PBSAD, PBSADA_RaRb, MUL, MAC, DIV, MMU
|
||
|
|
;; Require operands at EX.
|
||
|
|
;; ALU_SHIFT_Rb
|
||
|
|
;; An ALU-SHIFT instruction consists of a shift micro-operation followed
|
||
|
|
;; by an arithmetic micro-operation. The operand Rb is used by the first
|
||
|
|
;; micro-operation, and there are some latencies if data dependency occurs.
|
||
|
|
;; MAC_RaRb
|
||
|
|
;; A MAC instruction does multiplication at EX and does accumulation at MM,
|
||
|
|
;; so the operand Rt is required at MM, and operands Ra and Rb are required
|
||
|
|
;; at EX.
|
||
|
|
;; ADDR_IN
|
||
|
|
;; If an instruction requires an address as its input operand, the address
|
||
|
|
;; is required at EX.
|
||
|
|
;; ST
|
||
|
|
;; A store instruction requires its data at MM.
|
||
|
|
;; SMW(N, M)
|
||
|
|
;; There are N micro-operations within an instruction that stores multiple
|
||
|
|
;; words. Each M-th micro-operation requires its data at MM.
|
||
|
|
;; BR
|
||
|
|
;; If a branch instruction is conditional, its input data is required at EX.
|
||
|
|
|
||
|
|
;; LD, MUL, MAC, DIV
|
||
|
|
;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU
|
||
|
|
(define_bypass 2
|
||
|
|
"nds_n9_3r2w_load,\
|
||
|
|
nds_n9_3r2w_mul_fast1, nds_n9_3r2w_mul_fast2, nds_n9_3r2w_mul_slow,\
|
||
|
|
nds_n9_3r2w_mac_fast1, nds_n9_3r2w_mac_fast2, nds_n9_3r2w_mac_slow,\
|
||
|
|
nds_n9_3r2w_div"
|
||
|
|
"nds_n9_3r2w_alu, nds_n9_3r2w_alu_shift,\
|
||
|
|
nds_n9_3r2w_pbsad, nds_n9_3r2w_pbsada,\
|
||
|
|
nds_n9_3r2w_mul_fast1, nds_n9_3r2w_mul_fast2, nds_n9_3r2w_mul_slow,\
|
||
|
|
nds_n9_3r2w_mac_fast1, nds_n9_3r2w_mac_fast2, nds_n9_3r2w_mac_slow,\
|
||
|
|
nds_n9_3r2w_branch,\
|
||
|
|
nds_n9_3r2w_div,\
|
||
|
|
nds_n9_3r2w_load,nds_n9_3r2w_store,\
|
||
|
|
nds_n9_3r2w_load_multiple_1,nds_n9_3r2w_load_multiple_2, nds_n9_3r2w_load_multiple_3,\
|
||
|
|
nds_n9_3r2w_load_multiple_4,nds_n9_3r2w_load_multiple_5, nds_n9_3r2w_load_multiple_6,\
|
||
|
|
nds_n9_3r2w_load_multiple_7,nds_n9_3r2w_load_multiple_8, nds_n9_3r2w_load_multiple_12,\
|
||
|
|
nds_n9_3r2w_store_multiple_1,nds_n9_3r2w_store_multiple_2, nds_n9_3r2w_store_multiple_3,\
|
||
|
|
nds_n9_3r2w_store_multiple_4,nds_n9_3r2w_store_multiple_5, nds_n9_3r2w_store_multiple_6,\
|
||
|
|
nds_n9_3r2w_store_multiple_7,nds_n9_3r2w_store_multiple_8, nds_n9_3r2w_store_multiple_12,\
|
||
|
|
nds_n9_3r2w_mmu"
|
||
|
|
"nds32_n9_3r2w_mm_to_ex_p"
|
||
|
|
)
|
||
|
|
|
||
|
|
;; LMW(N, N)
|
||
|
|
;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU
|
||
|
|
(define_bypass 2
|
||
|
|
"nds_n9_3r2w_load_multiple_1,nds_n9_3r2w_load_multiple_2, nds_n9_3r2w_load_multiple_3,\
|
||
|
|
nds_n9_3r2w_load_multiple_4,nds_n9_3r2w_load_multiple_5, nds_n9_3r2w_load_multiple_6,\
|
||
|
|
nds_n9_3r2w_load_multiple_7,nds_n9_3r2w_load_multiple_8, nds_n9_3r2w_load_multiple_12"
|
||
|
|
"nds_n9_3r2w_alu, nds_n9_3r2w_alu_shift,\
|
||
|
|
nds_n9_3r2w_pbsad, nds_n9_3r2w_pbsada,\
|
||
|
|
nds_n9_3r2w_mul_fast1, nds_n9_3r2w_mul_fast2, nds_n9_3r2w_mul_slow,\
|
||
|
|
nds_n9_3r2w_mac_fast1, nds_n9_3r2w_mac_fast2, nds_n9_3r2w_mac_slow,\
|
||
|
|
nds_n9_3r2w_branch,\
|
||
|
|
nds_n9_3r2w_div,\
|
||
|
|
nds_n9_3r2w_load,nds_n9_3r2w_store,\
|
||
|
|
nds_n9_3r2w_load_multiple_1,nds_n9_3r2w_load_multiple_2, nds_n9_3r2w_load_multiple_3,\
|
||
|
|
nds_n9_3r2w_load_multiple_4,nds_n9_3r2w_load_multiple_5, nds_n9_3r2w_load_multiple_6,\
|
||
|
|
nds_n9_3r2w_load_multiple_7,nds_n9_3r2w_load_multiple_8, nds_n9_3r2w_load_multiple_12,\
|
||
|
|
nds_n9_3r2w_store_multiple_1,nds_n9_3r2w_store_multiple_2, nds_n9_3r2w_store_multiple_3,\
|
||
|
|
nds_n9_3r2w_store_multiple_4,nds_n9_3r2w_store_multiple_5, nds_n9_3r2w_store_multiple_6,\
|
||
|
|
nds_n9_3r2w_store_multiple_7,nds_n9_3r2w_store_multiple_8, nds_n9_3r2w_store_multiple_12,\
|
||
|
|
nds_n9_3r2w_mmu"
|
||
|
|
"nds32_n9_last_load_to_ex_p"
|
||
|
|
)
|