333 lines
11 KiB
Markdown
333 lines
11 KiB
Markdown
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;; GCC machine description for IA-64 synchronization instructions.
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;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Conversion to C++11 memory model based on
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;; http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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(define_mode_iterator IMODE [QI HI SI DI])
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(define_mode_iterator I124MODE [QI HI SI])
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(define_mode_iterator I48MODE [SI DI])
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(define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
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(define_code_iterator FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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(define_expand "mem_thread_fence"
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[(match_operand:SI 0 "const_int_operand" "")] ;; model
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""
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{
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if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
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emit_insn (gen_memory_barrier ());
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DONE;
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})
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MF))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*memory_barrier"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MF))]
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""
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"mf"
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[(set_attr "itanium_class" "syst_m")])
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(define_expand "atomic_load<mode>"
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[(match_operand:IMODE 0 "gr_register_operand" "") ;; output
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(match_operand:IMODE 1 "memory_operand" "") ;; memory
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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""
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
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/* Unless the memory model is relaxed, we want to emit ld.acq, which
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will happen automatically for volatile memories. */
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gcc_assert (is_mm_relaxed (model) || MEM_VOLATILE_P (operands[1]));
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emit_move_insn (operands[0], operands[1]);
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DONE;
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})
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(define_expand "atomic_store<mode>"
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[(match_operand:IMODE 0 "memory_operand" "") ;; memory
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(match_operand:IMODE 1 "gr_reg_or_0_operand" "") ;; input
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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""
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
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/* Unless the memory model is relaxed, we want to emit st.rel, which
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will happen automatically for volatile memories. */
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gcc_assert (is_mm_relaxed (model) || MEM_VOLATILE_P (operands[0]));
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emit_move_insn (operands[0], operands[1]);
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/* Sequentially consistent stores need a subsequent MF. See
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http://www.decadent.org.uk/pipermail/cpp-threads/2008-December/001952.html
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for a discussion of why a MF is needed here, but not for atomic_load. */
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if (is_mm_seq_cst (model))
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emit_insn (gen_memory_barrier ());
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DONE;
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})
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(define_expand "atomic_compare_and_swap<mode>"
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[(match_operand:DI 0 "gr_register_operand" "") ;; bool out
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(match_operand:IMODE 1 "gr_register_operand" "") ;; val out
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(match_operand:IMODE 2 "not_postinc_memory_operand" "") ;; memory
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(match_operand:IMODE 3 "gr_register_operand" "") ;; expected
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(match_operand:IMODE 4 "gr_reg_or_0_operand" "") ;; desired
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(match_operand:SI 5 "const_int_operand" "") ;; is_weak
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(match_operand:SI 6 "const_int_operand" "") ;; succ model
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(match_operand:SI 7 "const_int_operand" "")] ;; fail model
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""
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{
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/* No need to distinquish __sync from __atomic, so get base value. */
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enum memmodel model = memmodel_base (INTVAL (operands[6]));
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rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
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rtx dval, eval;
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eval = gen_reg_rtx (DImode);
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convert_move (eval, operands[3], 1);
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emit_move_insn (ccv, eval);
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if (<MODE>mode == DImode)
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dval = operands[1];
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else
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dval = gen_reg_rtx (DImode);
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switch (model)
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{
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case MEMMODEL_RELAXED:
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case MEMMODEL_ACQUIRE:
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case MEMMODEL_CONSUME:
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emit_insn (gen_cmpxchg_acq_<mode> (dval, operands[2], ccv, operands[4]));
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break;
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case MEMMODEL_RELEASE:
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emit_insn (gen_cmpxchg_rel_<mode> (dval, operands[2], ccv, operands[4]));
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break;
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case MEMMODEL_ACQ_REL:
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case MEMMODEL_SEQ_CST:
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emit_insn (gen_cmpxchg_rel_<mode> (dval, operands[2], ccv, operands[4]));
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emit_insn (gen_memory_barrier ());
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break;
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default:
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gcc_unreachable ();
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}
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if (<MODE>mode != DImode)
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emit_move_insn (operands[1], gen_lowpart (<MODE>mode, dval));
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emit_insn (gen_cstoredi4 (operands[0], gen_rtx_EQ (DImode, dval, eval),
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dval, eval));
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DONE;
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})
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(define_insn "cmpxchg_acq_<mode>"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(zero_extend:DI
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(match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
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(set (match_dup 1)
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(unspec:I124MODE
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[(match_dup 1)
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(match_operand:DI 2 "ar_ccv_reg_operand" "")
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(match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")]
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UNSPEC_CMPXCHG_ACQ))]
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""
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"cmpxchg<modesuffix>.acq %0 = %1, %r3, %2"
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[(set_attr "itanium_class" "sem")])
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(define_insn "cmpxchg_rel_<mode>"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(zero_extend:DI
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(match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
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(set (match_dup 1)
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(unspec:I124MODE
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[(match_dup 1)
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(match_operand:DI 2 "ar_ccv_reg_operand" "")
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(match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")]
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UNSPEC_CMPXCHG_REL))]
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""
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"cmpxchg<modesuffix>.rel %0 = %1, %r3, %2"
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[(set_attr "itanium_class" "sem")])
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(define_insn "cmpxchg_acq_di"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(match_operand:DI 1 "not_postinc_memory_operand" "+S"))
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(set (match_dup 1)
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(unspec:DI [(match_dup 1)
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(match_operand:DI 2 "ar_ccv_reg_operand" "")
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(match_operand:DI 3 "gr_reg_or_0_operand" "rO")]
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UNSPEC_CMPXCHG_ACQ))]
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""
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"cmpxchg8.acq %0 = %1, %r3, %2"
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[(set_attr "itanium_class" "sem")])
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(define_insn "cmpxchg_rel_di"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(match_operand:DI 1 "not_postinc_memory_operand" "+S"))
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(set (match_dup 1)
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(unspec:DI [(match_dup 1)
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(match_operand:DI 2 "ar_ccv_reg_operand" "")
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(match_operand:DI 3 "gr_reg_or_0_operand" "rO")]
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UNSPEC_CMPXCHG_REL))]
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""
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"cmpxchg8.rel %0 = %1, %r3, %2"
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[(set_attr "itanium_class" "sem")])
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(define_expand "atomic_exchange<mode>"
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[(match_operand:IMODE 0 "gr_register_operand" "") ;; output
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(match_operand:IMODE 1 "not_postinc_memory_operand" "") ;; memory
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(match_operand:IMODE 2 "gr_reg_or_0_operand" "") ;; input
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(match_operand:SI 3 "const_int_operand" "")] ;; succ model
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""
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{
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/* No need to distinquish __sync from __atomic, so get base value. */
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enum memmodel model = memmodel_base (INTVAL (operands[3]));
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switch (model)
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{
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case MEMMODEL_RELAXED:
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case MEMMODEL_ACQUIRE:
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case MEMMODEL_CONSUME:
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break;
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case MEMMODEL_RELEASE:
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case MEMMODEL_ACQ_REL:
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case MEMMODEL_SEQ_CST:
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emit_insn (gen_memory_barrier ());
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break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen_xchg_acq_<mode> (operands[0], operands[1], operands[2]));
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DONE;
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})
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;; Note that XCHG is always memory model acquire.
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(define_insn "xchg_acq_<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "=r")
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(match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
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(set (match_dup 1)
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(match_operand:IMODE 2 "gr_reg_or_0_operand" "rO"))]
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""
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"xchg<modesuffix> %0 = %1, %r2"
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[(set_attr "itanium_class" "sem")])
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(define_expand "atomic_<fetchop_name><mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "")
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(FETCHOP:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" "")))
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(use (match_operand:SI 2 "const_int_operand" ""))]
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""
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{
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ia64_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL,
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(enum memmodel) INTVAL (operands[2]));
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DONE;
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})
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(define_expand "atomic_nand<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "")
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(not:IMODE
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(and:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" ""))))
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(use (match_operand:SI 2 "const_int_operand" ""))]
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""
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{
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ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL,
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(enum memmodel) INTVAL (operands[2]));
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DONE;
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})
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(define_expand "atomic_fetch_<fetchop_name><mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(FETCHOP:IMODE
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(match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "nonmemory_operand" "")))
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(use (match_operand:SI 3 "const_int_operand" ""))]
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""
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{
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ia64_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL,
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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})
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(define_expand "atomic_fetch_nand<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(not:IMODE
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(and:IMODE (match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "nonmemory_operand" ""))))
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(use (match_operand:SI 3 "const_int_operand" ""))]
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""
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{
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ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL,
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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})
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(define_expand "atomic_<fetchop_name>_fetch<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(FETCHOP:IMODE
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(match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "nonmemory_operand" "")))
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(use (match_operand:SI 3 "const_int_operand" ""))]
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""
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{
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ia64_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0],
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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})
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(define_expand "atomic_nand_fetch<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(not:IMODE
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(and:IMODE (match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "nonmemory_operand" ""))))
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(use (match_operand:SI 3 "const_int_operand" ""))]
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""
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{
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ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0],
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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})
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(define_insn "fetchadd_acq_<mode>"
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[(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
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(match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
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(set (match_dup 1)
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(unspec:I48MODE [(match_dup 1)
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(match_operand:I48MODE 2 "fetchadd_operand" "n")]
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UNSPEC_FETCHADD_ACQ))]
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""
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"fetchadd<modesuffix>.acq %0 = %1, %2"
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[(set_attr "itanium_class" "sem")])
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(define_insn "fetchadd_rel_<mode>"
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[(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
|
||
|
|
(match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
|
||
|
|
(set (match_dup 1)
|
||
|
|
(unspec:I48MODE [(match_dup 1)
|
||
|
|
(match_operand:I48MODE 2 "fetchadd_operand" "n")]
|
||
|
|
UNSPEC_FETCHADD_REL))]
|
||
|
|
""
|
||
|
|
"fetchadd<modesuffix>.rel %0 = %1, %2"
|
||
|
|
[(set_attr "itanium_class" "sem")])
|