192 lines
7.1 KiB
Markdown
192 lines
7.1 KiB
Markdown
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;; Faraday FA626TE Pipeline Description
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;; Copyright (C) 2010-2021 Free Software Foundation, Inc.
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;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it under
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;; the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 3, or (at your option) any later
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;; version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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;; for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>. */
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;; These descriptions are based on the information contained in the
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;; FMP626 Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
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;; Pipeline architecture
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;; S E M W(Q1) Q2
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;; ___________________________________________
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;; shifter alu
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;; mul1 mul2 mul3
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;; ld/st1 ld/st2 ld/st3 ld/st4 ld/st5
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;; This automaton provides a pipeline description for the Faraday
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;; FMP626 core.
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;;
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;; The model given here assumes that the condition for all conditional
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;; instructions is "true", i.e., that all of the instructions are
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;; actually executed.
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(define_automaton "fmp626")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Pipelines
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; There is a single pipeline
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;;
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;; The ALU pipeline has fetch, decode, execute, memory, and
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;; write stages. We only need to model the execute, memory and write
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;; stages.
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(define_cpu_unit "fmp626_core" "fmp626")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions require two cycles to execute, and use the ALU
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;; pipeline in each of the three stages. The results are available
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;; after the execute stage has finished.
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;;
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;; If the destination register is the PC, the pipelines are stalled
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;; for several cycles. That case is not modeled here.
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;; ALU operations
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(define_insn_reservation "mp626_alu_op" 1
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
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logic_imm,logics_imm,logic_reg,logics_reg,\
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adc_imm,adcs_imm,adc_reg,adcs_reg,\
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adr,bfm,rev,\
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shift_imm,shift_reg,\
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mov_imm,mov_reg,mvn_imm,mvn_reg"))
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"fmp626_core")
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(define_insn_reservation "mp626_alu_shift_op" 2
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
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alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
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extend,\
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mov_shift,mov_shift_reg,\
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mvn_shift,mvn_shift_reg"))
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"fmp626_core")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn_reservation "mp626_mult1" 2
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "smulwy,smlawy,smulxy,smlaxy"))
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"fmp626_core")
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(define_insn_reservation "mp626_mult2" 2
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "mul,mla"))
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"fmp626_core")
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(define_insn_reservation "mp626_mult3" 3
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
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"fmp626_core*2")
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(define_insn_reservation "mp626_mult4" 4
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "smulls,smlals,umulls,umlals"))
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"fmp626_core*3")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/Store Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The models for load/store instructions do not accurately describe
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;; the difference between operations with a base register writeback
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;; (such as "ldm!"). These models assume that all memory references
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;; hit in dcache.
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(define_insn_reservation "mp626_load1_op" 5
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "load_4,load_byte"))
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"fmp626_core")
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(define_insn_reservation "mp626_load2_op" 6
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "load_8,load_12"))
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"fmp626_core*2")
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(define_insn_reservation "mp626_load3_op" 7
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "load_16"))
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"fmp626_core*3")
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(define_insn_reservation "mp626_store1_op" 0
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "store_4"))
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"fmp626_core")
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(define_insn_reservation "mp626_store2_op" 1
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "store_8,store_12"))
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"fmp626_core*2")
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(define_insn_reservation "mp626_store3_op" 2
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "store_16"))
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"fmp626_core*3")
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(define_bypass 1 "mp626_load1_op,mp626_load2_op,mp626_load3_op"
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"mp626_store1_op,mp626_store2_op,mp626_store3_op"
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"arm_no_early_store_addr_dep")
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(define_bypass 1 "mp626_alu_op,mp626_alu_shift_op,mp626_mult1,mp626_mult2,\
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mp626_mult3,mp626_mult4" "mp626_store1_op"
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"arm_no_early_store_addr_dep")
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(define_bypass 1 "mp626_alu_shift_op" "mp626_alu_op")
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(define_bypass 1 "mp626_alu_shift_op" "mp626_alu_shift_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 1 "mp626_mult1,mp626_mult2" "mp626_alu_shift_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 2 "mp626_mult3" "mp626_alu_shift_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 3 "mp626_mult4" "mp626_alu_shift_op"
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"arm_no_early_alu_shift_dep")
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(define_bypass 1 "mp626_mult1,mp626_mult2" "mp626_alu_op")
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(define_bypass 2 "mp626_mult3" "mp626_alu_op")
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(define_bypass 3 "mp626_mult4" "mp626_alu_op")
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(define_bypass 4 "mp626_load1_op" "mp626_alu_op")
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(define_bypass 5 "mp626_load2_op" "mp626_alu_op")
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(define_bypass 6 "mp626_load3_op" "mp626_alu_op")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch and Call Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch instructions are difficult to model accurately. The FMP626
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;; core can predict most branches. If the branch is predicted
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;; correctly, and predicted early enough, the branch can be completely
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;; eliminated from the instruction stream. Some branches can
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;; therefore appear to require zero cycle to execute. We assume that
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;; all branches are predicted correctly, and that the latency is
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;; therefore the minimum value.
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(define_insn_reservation "mp626_branch_op" 0
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "branch"))
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"fmp626_core")
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;; The latency for a call is actually the latency when the result is available.
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;; i.e. R0 ready for int return value.
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(define_insn_reservation "mp626_call_op" 1
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(and (eq_attr "tune" "fmp626")
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(eq_attr "type" "call"))
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"fmp626_core")
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