176 lines
6.3 KiB
Markdown
176 lines
6.3 KiB
Markdown
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;; ARMv8-A crypto patterns.
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;; Copyright (C) 2013-2021 Free Software Foundation, Inc.
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;; Contributed by ARM Ltd.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_insn "crypto_<crypto_pattern>"
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[(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
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(unspec:<crypto_mode>
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[(match_operand:<crypto_mode> 1 "register_operand" "w")]
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CRYPTO_AESMC))]
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"TARGET_CRYPTO"
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"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
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[(set_attr "type" "<crypto_type>")]
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)
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(define_insn "crypto_<crypto_pattern>"
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[(set (match_operand:V16QI 0 "register_operand" "=w")
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(unspec:V16QI
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[(xor:V16QI
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(match_operand:V16QI 1 "register_operand" "%0")
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(match_operand:V16QI 2 "register_operand" "w"))]
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CRYPTO_AES))]
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"TARGET_CRYPTO"
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"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2"
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[(set_attr "type" "<crypto_type>")]
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)
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;; When AESE/AESMC fusion is enabled we really want to keep the two together
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;; and enforce the register dependency without scheduling or register
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;; allocation messing up the order or introducing moves inbetween.
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;; Mash the two together during combine.
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(define_insn "*aarch32_crypto_aese_fused"
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[(set (match_operand:V16QI 0 "register_operand" "=w")
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(unspec:V16QI
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[(unspec:V16QI
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[(xor:V16QI
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(match_operand:V16QI 1 "register_operand" "%0")
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(match_operand:V16QI 2 "register_operand" "w"))]
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UNSPEC_AESE)]
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UNSPEC_AESMC))]
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"TARGET_CRYPTO
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&& arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)"
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"aese.8\\t%q0, %q2\;aesmc.8\\t%q0, %q0"
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[(set_attr "type" "crypto_aese")
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(set_attr "length" "8")]
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)
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;; When AESD/AESIMC fusion is enabled we really want to keep the two together
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;; and enforce the register dependency without scheduling or register
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;; allocation messing up the order or introducing moves inbetween.
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;; Mash the two together during combine.
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(define_insn "*aarch32_crypto_aesd_fused"
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[(set (match_operand:V16QI 0 "register_operand" "=w")
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(unspec:V16QI
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[(unspec:V16QI
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[(xor:V16QI
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(match_operand:V16QI 1 "register_operand" "%0")
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(match_operand:V16QI 2 "register_operand" "w"))]
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UNSPEC_AESD)]
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UNSPEC_AESIMC))]
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"TARGET_CRYPTO
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&& arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)"
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"aesd.8\\t%q0, %q2\;aesimc.8\\t%q0, %q0"
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[(set_attr "type" "crypto_aese")
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(set_attr "length" "8")]
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)
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(define_insn "crypto_<crypto_pattern>"
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[(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
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(unspec:<crypto_mode>
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[(match_operand:<crypto_mode> 1 "register_operand" "0")
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(match_operand:<crypto_mode> 2 "register_operand" "w")]
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CRYPTO_BINARY))]
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"TARGET_CRYPTO"
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"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2"
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[(set_attr "type" "<crypto_type>")]
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)
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(define_insn "crypto_<crypto_pattern>"
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[(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
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(unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 "register_operand" "0")
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(match_operand:<crypto_mode> 2 "register_operand" "w")
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(match_operand:<crypto_mode> 3 "register_operand" "w")]
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CRYPTO_TERNARY))]
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"TARGET_CRYPTO"
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"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2, %q3"
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[(set_attr "type" "<crypto_type>")]
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)
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/* The vec_select operation always selects index 0 from the lower V2SI subreg
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of the V4SI, adjusted for endianness. Required due to neon_vget_lane and
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neon_set_lane that change the element ordering in memory for big-endian. */
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(define_expand "crypto_sha1h"
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[(set (match_operand:V4SI 0 "register_operand")
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(match_operand:V4SI 1 "register_operand"))]
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"TARGET_CRYPTO"
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{
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rtx op2 = GEN_INT (NEON_ENDIAN_LANE_N (V2SImode, 0));
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emit_insn (gen_crypto_sha1h_lb (operands[0], operands[1], op2));
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DONE;
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})
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(define_insn "crypto_sha1h_lb"
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[(set (match_operand:V4SI 0 "register_operand" "=w")
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(unspec:V4SI
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[(vec_select:SI
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(match_operand:V4SI 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")]))]
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UNSPEC_SHA1H))]
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"TARGET_CRYPTO && INTVAL (operands[2]) == NEON_ENDIAN_LANE_N (V2SImode, 0)"
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"sha1h.32\\t%q0, %q1"
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[(set_attr "type" "crypto_sha1_fast")]
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)
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(define_insn "crypto_vmullp64"
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[(set (match_operand:TI 0 "register_operand" "=w")
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(unspec:TI [(match_operand:DI 1 "register_operand" "w")
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(match_operand:DI 2 "register_operand" "w")]
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UNSPEC_VMULLP64))]
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"TARGET_CRYPTO"
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"vmull.p64\\t%q0, %P1, %P2"
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[(set_attr "type" "crypto_pmull")]
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)
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/* The vec_select operation always selects index 0 from the lower V2SI subreg
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of the V4SI, adjusted for endianness. Required due to neon_vget_lane and
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neon_set_lane that change the element ordering in memory for big-endian. */
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(define_expand "crypto_<crypto_pattern>"
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[(set (match_operand:V4SI 0 "register_operand")
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(unspec:<crypto_mode>
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[(match_operand:<crypto_mode> 1 "register_operand")
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(match_operand:<crypto_mode> 2 "register_operand")
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(match_operand:<crypto_mode> 3 "register_operand")]
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CRYPTO_SELECTING))]
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"TARGET_CRYPTO"
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{
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rtx op4 = GEN_INT (NEON_ENDIAN_LANE_N (V2SImode, 0));
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emit_insn (gen_crypto_<crypto_pattern>_lb
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(operands[0], operands[1], operands[2], operands[3], op4));
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DONE;
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})
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(define_insn "crypto_<crypto_pattern>_lb"
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[(set (match_operand:V4SI 0 "register_operand" "=w")
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(unspec:<crypto_mode>
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[(match_operand:<crypto_mode> 1 "register_operand" "0")
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(vec_select:SI
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(match_operand:<crypto_mode> 2 "register_operand" "w")
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(parallel [(match_operand:SI 4 "immediate_operand" "i")]))
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(match_operand:<crypto_mode> 3 "register_operand" "w")]
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CRYPTO_SELECTING))]
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"TARGET_CRYPTO && INTVAL (operands[4]) == NEON_ENDIAN_LANE_N (V2SImode, 0)"
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"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2, %q3"
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[(set_attr "type" "<crypto_type>")]
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)
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