219 lines
7.0 KiB
Markdown
219 lines
7.0 KiB
Markdown
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;; GCC machine description for ARC atomic instructions.
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;; Copyright (C) 2015-2021 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_mode_iterator QHSI [QI HI SI])
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(define_code_iterator atomicop [plus minus ior xor and])
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(define_code_attr atomic_optab
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[(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_ARC_MEMBAR))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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;; A compiler-only memory barrier for ARC700. Generic code, when
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;; checking for the existence of various named patterns, uses
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;; asm("":::"memory") when we don't need an actual instruction. For
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;; ARCHS, we use a hardware data memory barrier that waits for
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;; completion of current data memory operations before initiating
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;; similar data memory operations.
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(define_insn "*memory_barrier"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_ARC_MEMBAR))]
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""
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{
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if (TARGET_HS)
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{
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return "dmb\\t3";
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}
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else
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{
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return "";
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}
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}
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[(set_attr "type" "multi")
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(set_attr "length" "4")])
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(define_expand "atomic_compare_and_swap<mode>"
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[(match_operand:SI 0 "register_operand" "") ;; bool out
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(match_operand:QHSI 1 "register_operand" "") ;; val out
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(match_operand:QHSI 2 "mem_noofs_operand" "");; memory
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(match_operand:QHSI 3 "register_operand" "") ;; expected
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(match_operand:QHSI 4 "register_operand" "") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; mod_s
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(match_operand:SI 7 "const_int_operand")] ;; mod_f
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"TARGET_ATOMIC"
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{
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arc_expand_compare_and_swap (operands);
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DONE;
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})
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(define_insn_and_split "atomic_compare_and_swapsi_1"
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[(set (reg:CC_Z CC_REG) ;; bool out
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(unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ARC_CAS))
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(match_operand:SI 1 "mem_noofs_operand" "+ATO")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:SI
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[(match_operand:SI 2 "register_operand" "r") ;; expect
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(match_operand:SI 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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VUNSPEC_ARC_CAS))]
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"TARGET_ATOMIC"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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arc_split_compare_and_swap (operands);
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DONE;
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})
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(define_insn "arc_load_exclusivesi"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI
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[(match_operand:SI 1 "mem_noofs_operand" "ATO")]
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VUNSPEC_ARC_LL))]
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"TARGET_ATOMIC"
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"llock %0,%1"
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[(set_attr "type" "load")
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(set_attr "iscompact" "false")
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(set_attr "predicable" "no")
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(set_attr "length" "*")])
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(define_insn "arc_store_exclusivesi"
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[(set (match_operand:SI 0 "mem_noofs_operand" "=ATO")
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(unspec_volatile:SI[(match_operand:SI 1 "register_operand" "r")]
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VUNSPEC_ARC_SC))
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(clobber (reg:CC_Z CC_REG))]
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"TARGET_ATOMIC"
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"scond %1,%0"
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[(set_attr "type" "store")
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(set_attr "iscompact" "false")
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(set_attr "predicable" "no")
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(set_attr "length" "*")])
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(define_expand "atomic_exchangesi"
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[(match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "mem_noofs_operand" "")
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(match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "const_int_operand" "")]
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"TARGET_ARC700 || TARGET_V2"
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[3]);
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if (model == MEMMODEL_SEQ_CST)
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emit_insn (gen_sync (const1_rtx));
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emit_insn (gen_exchangesi (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "exchangesi"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI [(match_operand:SI 1 "mem_noofs_operand" "+ATO")]
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VUNSPEC_ARC_EX))
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(set (match_dup 1)
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(match_operand:SI 2 "register_operand" "0"))]
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""
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"ex %0,%1"
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[(set_attr "type" "load")
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(set_attr "iscompact" "false")
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(set_attr "predicable" "no")
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(set_attr "length" "*")])
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(define_expand "atomic_<atomic_optab>si"
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[(match_operand:SI 0 "mem_noofs_operand" "") ;; memory
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(atomicop:SI (match_dup 0)
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(match_operand:SI 1 "register_operand" "")) ;; operand
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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"TARGET_ATOMIC"
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{
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arc_expand_atomic_op (<CODE>, operands[0], operands[1],
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NULL_RTX, NULL_RTX, operands[2]);
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DONE;
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})
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(define_expand "atomic_nandsi"
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[(match_operand:SI 0 "mem_noofs_operand" "") ;; memory
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(match_operand:SI 1 "register_operand" "") ;; operand
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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"TARGET_ATOMIC"
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{
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arc_expand_atomic_op (NOT, operands[0], operands[1],
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NULL_RTX, NULL_RTX, operands[2]);
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DONE;
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})
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(define_expand "atomic_fetch_<atomic_optab>si"
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[(match_operand:SI 0 "register_operand" "") ;; output
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(match_operand:SI 1 "mem_noofs_operand" "") ;; memory
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(atomicop:SI (match_dup 1)
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(match_operand:SI 2 "register_operand" "")) ;; operand
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(match_operand:SI 3 "const_int_operand" "")] ;; model
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"TARGET_ATOMIC"
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{
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arc_expand_atomic_op (<CODE>, operands[1], operands[2],
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operands[0], NULL_RTX, operands[3]);
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DONE;
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})
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(define_expand "atomic_fetch_nandsi"
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[(match_operand:SI 0 "register_operand" "") ;; output
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(match_operand:SI 1 "mem_noofs_operand" "") ;; memory
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(match_operand:SI 2 "register_operand" "") ;; operand
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(match_operand:SI 3 "const_int_operand" "")] ;; model
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"TARGET_ATOMIC"
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{
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arc_expand_atomic_op (NOT, operands[1], operands[2],
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operands[0], NULL_RTX, operands[3]);
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DONE;
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})
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(define_expand "atomic_<atomic_optab>_fetchsi"
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[(match_operand:SI 0 "register_operand" "") ;; output
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(match_operand:SI 1 "mem_noofs_operand" "") ;; memory
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(atomicop:SI (match_dup 1)
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(match_operand:SI 2 "register_operand" "")) ;; operand
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(match_operand:SI 3 "const_int_operand" "")] ;; model
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"TARGET_ATOMIC"
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{
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arc_expand_atomic_op (<CODE>, operands[1], operands[2],
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NULL_RTX, operands[0], operands[3]);
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DONE;
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})
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(define_expand "atomic_nand_fetchsi"
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[(match_operand:SI 0 "register_operand" "") ;; output
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(match_operand:SI 1 "mem_noofs_operand" "") ;; memory
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(match_operand:SI 2 "register_operand" "") ;; operand
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(match_operand:SI 3 "const_int_operand" "")] ;; model
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"TARGET_ATOMIC"
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{
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arc_expand_atomic_op (NOT, operands[1], operands[2],
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NULL_RTX, operands[0], operands[3]);
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DONE;
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})
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