344 lines
11 KiB
Markdown
344 lines
11 KiB
Markdown
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;; GCC machine description for Alpha synchronization instructions.
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;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_code_iterator FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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(define_code_attr fetchop_pred
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[(plus "add_operand") (minus "reg_or_8bit_operand")
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(ior "or_operand") (xor "or_operand") (and "and_operand")])
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(define_code_attr fetchop_constr
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[(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "rINM")])
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MB))]
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""
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*memory_barrier"
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[(set (match_operand:BLK 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MB))]
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""
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"mb"
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[(set_attr "type" "mb")])
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(define_insn "@load_locked_<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(unspec_volatile:I48MODE
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[(match_operand:I48MODE 1 "memory_operand" "m")]
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UNSPECV_LL))]
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""
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"ld<modesuffix>_l %0,%1"
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[(set_attr "type" "ld_l")])
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(define_insn "@store_conditional_<mode>"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
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(set (match_operand:I48MODE 1 "memory_operand" "=m")
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(match_operand:I48MODE 2 "reg_or_0_operand" "0"))]
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""
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"st<modesuffix>_c %0,%1"
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[(set_attr "type" "st_c")])
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;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
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;; the lock is cleared by a normal load or store. This means we cannot
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;; expand a ll/sc sequence before reload, lest a register spill is
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;; inserted inside the sequence. It is also UNPREDICTABLE whether the
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;; lock is cleared by a TAKEN branch. This means that we cannot expand
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;; a ll/sc sequence containing a branch (i.e. compare-and-swap) until after
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;; the final basic-block reordering pass.
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(define_expand "atomic_compare_and_swap<mode>"
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[(parallel
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[(set (match_operand:DI 0 "register_operand") ;; bool out
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(unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_operand:I48MODE 1 "register_operand") ;; val out
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(unspec_volatile:I48MODE [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_operand:I48MODE 2 "memory_operand") ;; memory
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(unspec_volatile:I48MODE
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[(match_dup 2)
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(match_operand:I48MODE 3 "reg_or_8bit_operand") ;; expected
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(match_operand:I48MODE 4 "add_operand") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; succ model
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(match_operand:SI 7 "const_int_operand")] ;; fail model
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UNSPECV_CMPXCHG))])]
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""
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{
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if (<MODE>mode == SImode)
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{
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operands[3] = convert_modes (DImode, SImode, operands[3], 0);
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operands[4] = convert_modes (DImode, SImode, operands[4], 0);
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}
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})
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(define_insn_and_split "*atomic_compare_and_swap<mode>"
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[(set (match_operand:DI 0 "register_operand" "=&r") ;; bool out
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(unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_operand:I48MODE 1 "register_operand" "=&r") ;; val out
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(unspec_volatile:I48MODE [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_operand:I48MODE 2 "memory_operand" "+m") ;; memory
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(unspec_volatile:I48MODE
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[(match_dup 2)
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(match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected
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(match_operand:DI 4 "add_operand" "rKL") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; succ model
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(match_operand:SI 7 "const_int_operand")] ;; fail model
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UNSPECV_CMPXCHG))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_compare_and_swap (operands);
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_expand "atomic_compare_and_swap<mode>"
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[(match_operand:DI 0 "register_operand") ;; bool out
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(match_operand:I12MODE 1 "register_operand") ;; val out
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(match_operand:I12MODE 2 "mem_noofs_operand") ;; memory
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(match_operand:I12MODE 3 "register_operand") ;; expected
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(match_operand:I12MODE 4 "add_operand") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; succ model
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(match_operand:SI 7 "const_int_operand")] ;; fail model
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""
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{
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alpha_expand_compare_and_swap_12 (operands);
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DONE;
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})
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(define_insn_and_split "@atomic_compare_and_swap<mode>_1"
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[(set (match_operand:DI 0 "register_operand" "=&r") ;; bool out
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(unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_operand:DI 1 "register_operand" "=&r") ;; val out
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(zero_extend:DI
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(unspec_volatile:I12MODE [(const_int 0)] UNSPECV_CMPXCHG)))
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(set (match_operand:I12MODE 2 "mem_noofs_operand" "+w") ;; memory
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(unspec_volatile:I12MODE
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[(match_dup 2)
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(match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected
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(match_operand:DI 4 "reg_or_0_operand" "rJ") ;; desired
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(match_operand:DI 5 "register_operand" "r") ;; align
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(match_operand:SI 6 "const_int_operand") ;; is_weak
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(match_operand:SI 7 "const_int_operand") ;; succ model
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(match_operand:SI 8 "const_int_operand")] ;; fail model
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UNSPECV_CMPXCHG))
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(clobber (match_scratch:DI 9 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_compare_and_swap_12 (operands);
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_exchange<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r") ;; output
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(match_operand:I48MODE 1 "memory_operand" "+m")) ;; memory
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(set (match_dup 1)
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(unspec:I48MODE
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[(match_operand:I48MODE 2 "add_operand" "rKL") ;; input
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPEC_XCHG))
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(clobber (match_scratch:I48MODE 4 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_exchange (operands);
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_expand "atomic_exchange<mode>"
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[(match_operand:I12MODE 0 "register_operand") ;; output
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(match_operand:I12MODE 1 "mem_noofs_operand") ;; memory
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(match_operand:I12MODE 2 "reg_or_0_operand") ;; input
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(match_operand:SI 3 "const_int_operand")] ;; model
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""
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{
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alpha_expand_atomic_exchange_12 (operands);
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DONE;
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})
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(define_insn_and_split "@atomic_exchange<mode>_1"
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[(set (match_operand:DI 0 "register_operand" "=&r") ;; output
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(zero_extend:DI
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(match_operand:I12MODE 1 "mem_noofs_operand" "+w"))) ;; memory
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(set (match_dup 1)
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(unspec:I12MODE
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[(match_operand:DI 2 "reg_or_8bit_operand" "rI") ;; input
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(match_operand:DI 3 "register_operand" "r") ;; align
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(match_operand:SI 4 "const_int_operand")] ;; model
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UNSPEC_XCHG))
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(clobber (match_scratch:DI 5 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_exchange_12 (operands);
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_<fetchop_name><mode>"
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[(set (match_operand:I48MODE 0 "memory_operand" "+m")
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(unspec:I48MODE
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[(FETCHOP:I48MODE (match_dup 0)
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(match_operand:I48MODE 1 "<fetchop_pred>" "<fetchop_constr>"))
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(match_operand:SI 2 "const_int_operand")]
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_op (<CODE>, operands[0], operands[1],
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NULL, NULL, operands[3],
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(enum memmodel) INTVAL (operands[2]));
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_nand<mode>"
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[(set (match_operand:I48MODE 0 "memory_operand" "+m")
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(unspec:I48MODE
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[(not:I48MODE
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(and:I48MODE (match_dup 0)
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(match_operand:I48MODE 1 "register_operand" "r")))
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(match_operand:SI 2 "const_int_operand")]
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_op (NOT, operands[0], operands[1],
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NULL, NULL, operands[3],
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(enum memmodel) INTVAL (operands[2]));
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_fetch_<fetchop_name><mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(unspec:I48MODE
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[(FETCHOP:I48MODE (match_dup 1)
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(match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>"))
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(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 4 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_op (<CODE>, operands[1], operands[2],
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operands[0], NULL, operands[4],
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_fetch_nand<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(unspec:I48MODE
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[(not:I48MODE
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(and:I48MODE (match_dup 1)
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(match_operand:I48MODE 2 "register_operand" "r")))
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(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 4 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_op (NOT, operands[1], operands[2],
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operands[0], NULL, operands[4],
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_<fetchop_name>_fetch<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(FETCHOP:I48MODE
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(match_operand:I48MODE 1 "memory_operand" "+m")
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(match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>")))
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(set (match_dup 1)
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(unspec:I48MODE
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[(FETCHOP:I48MODE (match_dup 1) (match_dup 2))
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(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 4 "=&r"))]
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""
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"#"
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"epilogue_completed"
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[(const_int 0)]
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{
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alpha_split_atomic_op (<CODE>, operands[1], operands[2],
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NULL, operands[0], operands[4],
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(enum memmodel) INTVAL (operands[3]));
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DONE;
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}
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[(set_attr "type" "multi")])
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(define_insn_and_split "atomic_nand_fetch<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(not:I48MODE
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||
|
|
(and:I48MODE (match_operand:I48MODE 1 "memory_operand" "+m")
|
||
|
|
(match_operand:I48MODE 2 "register_operand" "r"))))
|
||
|
|
(set (match_dup 1)
|
||
|
|
(unspec:I48MODE
|
||
|
|
[(not:I48MODE (and:I48MODE (match_dup 1) (match_dup 2)))
|
||
|
|
(match_operand:SI 3 "const_int_operand")]
|
||
|
|
UNSPEC_ATOMIC))
|
||
|
|
(clobber (match_scratch:I48MODE 4 "=&r"))]
|
||
|
|
""
|
||
|
|
"#"
|
||
|
|
"epilogue_completed"
|
||
|
|
[(const_int 0)]
|
||
|
|
{
|
||
|
|
alpha_split_atomic_op (NOT, operands[1], operands[2],
|
||
|
|
NULL, operands[0], operands[4],
|
||
|
|
(enum memmodel) INTVAL (operands[3]));
|
||
|
|
DONE;
|
||
|
|
}
|
||
|
|
[(set_attr "type" "multi")])
|