329 lines
16 KiB
Plaintext
329 lines
16 KiB
Plaintext
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// i386 register table.
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// Copyright (C) 2007-2022 Free Software Foundation, Inc.
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//
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// This file is part of the GNU opcodes library.
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//
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// This library is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3, or (at your option)
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// any later version.
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//
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// It is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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// License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GAS; see the file COPYING. If not, write to the Free
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// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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// 8 bit regs
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al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
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cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
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dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
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bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
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ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
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ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
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dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
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bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
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axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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// 16 bit regs
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ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
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cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
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dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
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bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
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bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
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// 32 bit regs
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eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
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ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
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ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
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rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
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rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
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// Vector mask registers.
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k0, Class=RegMask, 0, 0, 93, 118
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k1, Class=RegMask, 0, 1, 94, 119
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k2, Class=RegMask, 0, 2, 95, 120
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k3, Class=RegMask, 0, 3, 96, 121
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k4, Class=RegMask, 0, 4, 97, 122
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k5, Class=RegMask, 0, 5, 98, 123
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k6, Class=RegMask, 0, 6, 99, 124
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k7, Class=RegMask, 0, 7, 100, 125
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// Segment registers.
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es, Class=SReg, 0, 0, 40, 50
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cs, Class=SReg, 0, 1, 41, 51
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ss, Class=SReg, 0, 2, 42, 52
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ds, Class=SReg, 0, 3, 43, 53
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fs, Class=SReg, 0, 4, 44, 54
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gs, Class=SReg, 0, 5, 45, 55
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flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
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// Control registers.
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cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
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cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
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cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
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cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
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cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
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cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
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cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
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cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
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cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
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cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
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cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
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cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
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cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
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cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
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cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
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cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
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// Debug registers.
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db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
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db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
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db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
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db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
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db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
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db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
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db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
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db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
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db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
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db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
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db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
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db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
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db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
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db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
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db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
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db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
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dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
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dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
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dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
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dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
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dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
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dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
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dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
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dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
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dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
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dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
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dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
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dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
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dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
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dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
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dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
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dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
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// Test registers.
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tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
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tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
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tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
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tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
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tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
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tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
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tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
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tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
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// MMX and simd registers.
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mm0, Class=RegMMX, 0, 0, 29, 41
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mm1, Class=RegMMX, 0, 1, 30, 42
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mm2, Class=RegMMX, 0, 2, 31, 43
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mm3, Class=RegMMX, 0, 3, 32, 44
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mm4, Class=RegMMX, 0, 4, 33, 45
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mm5, Class=RegMMX, 0, 5, 34, 46
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mm6, Class=RegMMX, 0, 6, 35, 47
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mm7, Class=RegMMX, 0, 7, 36, 48
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xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
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xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
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xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
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xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
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xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
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xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
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xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
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xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
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xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
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xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
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xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
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xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
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xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
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xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
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xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
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xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
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xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
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xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
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xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
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xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
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xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
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xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
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xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
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xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
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xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
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xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
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xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
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xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
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xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
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xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
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xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
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xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
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// AVX registers.
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ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
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ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
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ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
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ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
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ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
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ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
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ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
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ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
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ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
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ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
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ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
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ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
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ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
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ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
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ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
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ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
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ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
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ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
|
||
|
|
ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
|
||
|
|
ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
|
||
|
|
ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
|
||
|
|
ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
|
||
|
|
ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
|
||
|
|
ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
|
||
|
|
ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||
|
|
ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||
|
|
ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||
|
|
ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||
|
|
ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||
|
|
ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||
|
|
ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||
|
|
ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||
|
|
// AVX512 registers.
|
||
|
|
zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
|
||
|
|
zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
|
||
|
|
zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
|
||
|
|
zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
|
||
|
|
zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
|
||
|
|
zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
|
||
|
|
zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
|
||
|
|
zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
|
||
|
|
zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
|
||
|
|
zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
|
||
|
|
zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
|
||
|
|
zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
|
||
|
|
zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
|
||
|
|
zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
|
||
|
|
zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
|
||
|
|
zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
|
||
|
|
zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
|
||
|
|
zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
|
||
|
|
zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
|
||
|
|
zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
|
||
|
|
zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
|
||
|
|
zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
|
||
|
|
zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
|
||
|
|
zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
|
||
|
|
zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||
|
|
zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||
|
|
zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||
|
|
zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||
|
|
zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||
|
|
zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||
|
|
zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||
|
|
zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||
|
|
// TMM registers for AMX
|
||
|
|
tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
|
||
|
|
tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
|
||
|
|
tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
|
||
|
|
tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
|
||
|
|
tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
|
||
|
|
tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
|
||
|
|
tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
|
||
|
|
tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
|
||
|
|
// Bound registers for MPX
|
||
|
|
bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
|
||
|
|
bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
|
||
|
|
bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
|
||
|
|
bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
|
||
|
|
// No Class=Reg will make these registers rejected for all purposes except
|
||
|
|
// for addressing. This saves creating one extra type for RIP/EIP.
|
||
|
|
rip, Qword, RegRex64, RegIP, Dw2Inval, 16
|
||
|
|
eip, Dword, RegRex64, RegIP, 8, Dw2Inval
|
||
|
|
// No Class=Reg will make these registers rejected for all purposes except
|
||
|
|
// for addressing.
|
||
|
|
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
|
||
|
|
eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
|
||
|
|
// fp regs. No need for an explicit st(0) here.
|
||
|
|
st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
|
||
|
|
st(1), Class=Reg|Tbyte, 0, 1, 12, 34
|
||
|
|
st(2), Class=Reg|Tbyte, 0, 2, 13, 35
|
||
|
|
st(3), Class=Reg|Tbyte, 0, 3, 14, 36
|
||
|
|
st(4), Class=Reg|Tbyte, 0, 4, 15, 37
|
||
|
|
st(5), Class=Reg|Tbyte, 0, 5, 16, 38
|
||
|
|
st(6), Class=Reg|Tbyte, 0, 6, 17, 39
|
||
|
|
st(7), Class=Reg|Tbyte, 0, 7, 18, 40
|
||
|
|
// Pseudo-register names only used in .cfi_* directives
|
||
|
|
eflags, 0, 0, 0, 9, 49
|
||
|
|
rflags, 0, 0, 0, Dw2Inval, 49
|
||
|
|
fs.base, 0, 0, 0, Dw2Inval, 58
|
||
|
|
gs.base, 0, 0, 0, Dw2Inval, 59
|
||
|
|
tr, 0, 0, 0, 48, 62
|
||
|
|
ldtr, 0, 0, 0, 49, 63
|
||
|
|
// st0...7 for backward compatibility
|
||
|
|
st0, 0, 0, 0, 11, 33
|
||
|
|
st1, 0, 0, 1, 12, 34
|
||
|
|
st2, 0, 0, 2, 13, 35
|
||
|
|
st3, 0, 0, 3, 14, 36
|
||
|
|
st4, 0, 0, 4, 15, 37
|
||
|
|
st5, 0, 0, 5, 16, 38
|
||
|
|
st6, 0, 0, 6, 17, 39
|
||
|
|
st7, 0, 0, 7, 18, 40
|
||
|
|
fcw, 0, 0, 0, 37, 65
|
||
|
|
fsw, 0, 0, 0, 38, 66
|
||
|
|
mxcsr, 0, 0, 0, 39, 64
|