69 lines
1.2 KiB
Verilog
69 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
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module clk_tb;
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reg clk, rst_n;
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initial begin
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clk = 0;
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end
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always #1 clk = ~clk;
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initial begin
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rst_n = 1;
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#1 rst_n = 0;
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#1 rst_n = 1;
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end
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wire clk_uart_tx;
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wire tx_pin;
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wire tx_busy;
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reg rx_pin;
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wire[7:0] rx_data;
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wire rx_rdy;
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uart_top uart_top_inst(
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.clk(clk),
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.rstn(rst_n),
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.rx_pin(rx_pin)
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);
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parameter delay = 100;
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reg [7:0] tx_data;
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initial begin
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rx_pin = 1;
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#10;
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tx_data = 8'h55;
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rx_pin = 1'b0;#delay;
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rx_pin = tx_data[0] ;#delay;
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rx_pin = tx_data[1] ;#delay;
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rx_pin = tx_data[2] ;#delay;
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rx_pin = tx_data[3] ;#delay;
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rx_pin = tx_data[4] ;#delay;
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rx_pin = tx_data[5] ;#delay;
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rx_pin = tx_data[6] ;#delay;
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rx_pin = tx_data[7] ;#delay;
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rx_pin = 1'b1 ;#delay;
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// #delay;
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tx_data = 8'hAA;
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rx_pin = 1'b0 ;#delay;
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rx_pin = tx_data[0] ;#delay;
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rx_pin = tx_data[1] ;#delay;
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rx_pin = tx_data[2] ;#delay;
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rx_pin = tx_data[3] ;#delay;
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rx_pin = tx_data[4] ;#delay;
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rx_pin = tx_data[5] ;#delay;
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rx_pin = tx_data[6] ;#delay;
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rx_pin = tx_data[7] ;#delay;
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rx_pin = 1'b1 ;#delay;
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#delay;
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end
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initial begin
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$dumpfile("uart_tb.vcd");
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$dumpvars(0, clk_tb);
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#100000 $finish;
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end
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endmodule |