217 lines
5.7 KiB
Plaintext
217 lines
5.7 KiB
Plaintext
|uart_top
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clk => clk.IN2
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rstn => rstn.IN2
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rx_pin => rx_pin.IN1
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tx_pin << uart_tx:uart_tx_c0.tx_pin
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|uart_top|uart_tx:uart_tx_c0
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clk => tx_ply_ok~reg0.CLK
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clk => data_reg[0].CLK
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clk => data_reg[1].CLK
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clk => data_reg[2].CLK
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clk => data_reg[3].CLK
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clk => data_reg[4].CLK
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clk => data_reg[5].CLK
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clk => data_reg[6].CLK
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clk => data_reg[7].CLK
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clk => tx_count[0].CLK
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clk => tx_count[1].CLK
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clk => tx_count[2].CLK
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clk => tx_count[3].CLK
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clk => count[0].CLK
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clk => count[1].CLK
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clk => count[2].CLK
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clk => count[3].CLK
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clk => count[4].CLK
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clk => count[5].CLK
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clk => tx_pin~reg0.CLK
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clk => state~5.DATAIN
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rstn => tx_ply_ok~reg0.ACLR
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rstn => data_reg[0].ACLR
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rstn => data_reg[1].ACLR
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rstn => data_reg[2].ACLR
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rstn => data_reg[3].ACLR
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rstn => data_reg[4].ACLR
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rstn => data_reg[5].ACLR
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rstn => data_reg[6].ACLR
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rstn => data_reg[7].ACLR
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rstn => tx_count[0].ACLR
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rstn => tx_count[1].ACLR
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rstn => tx_count[2].ACLR
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rstn => tx_count[3].ACLR
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rstn => count[0].ACLR
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rstn => count[1].ACLR
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rstn => count[2].ACLR
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rstn => count[3].ACLR
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rstn => count[4].ACLR
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rstn => count[5].ACLR
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rstn => tx_pin~reg0.PRESET
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rstn => state~7.DATAIN
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en => tx_pin.OUTPUTSELECT
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en => count.OUTPUTSELECT
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en => count.OUTPUTSELECT
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en => count.OUTPUTSELECT
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en => count.OUTPUTSELECT
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en => count.OUTPUTSELECT
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en => count.OUTPUTSELECT
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en => tx_count.OUTPUTSELECT
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en => tx_count.OUTPUTSELECT
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en => tx_count.OUTPUTSELECT
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en => tx_count.OUTPUTSELECT
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en => state.OUTPUTSELECT
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en => state.OUTPUTSELECT
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en => state.OUTPUTSELECT
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en => state.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => data_reg.OUTPUTSELECT
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en => tx_ply_ok.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => data_reg.OUTPUTSELECT
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tx_req_start => state.OUTPUTSELECT
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tx_req_start => state.OUTPUTSELECT
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tx_req_start => state.OUTPUTSELECT
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tx_req_start => state.OUTPUTSELECT
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tx_data[0] => data_reg.DATAB
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tx_data[1] => data_reg.DATAB
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tx_data[2] => data_reg.DATAB
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tx_data[3] => data_reg.DATAB
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tx_data[4] => data_reg.DATAB
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tx_data[5] => data_reg.DATAB
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tx_data[6] => data_reg.DATAB
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tx_data[7] => data_reg.DATAB
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tx_ply_ok <= tx_ply_ok~reg0.DB_MAX_OUTPUT_PORT_TYPE
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tx_busy <= <GND>
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tx_pin <= tx_pin~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|uart_top|uart_rx:uart_rx_c0
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clk => rx_data[0]~reg0.CLK
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clk => rx_data[1]~reg0.CLK
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clk => rx_data[2]~reg0.CLK
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clk => rx_data[3]~reg0.CLK
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clk => rx_data[4]~reg0.CLK
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clk => rx_data[5]~reg0.CLK
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clk => rx_data[6]~reg0.CLK
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clk => rx_data[7]~reg0.CLK
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clk => rx_reg[0].CLK
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clk => rx_reg[1].CLK
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clk => rx_reg[2].CLK
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clk => rx_reg[3].CLK
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clk => rx_reg[4].CLK
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clk => rx_reg[5].CLK
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clk => rx_reg[6].CLK
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clk => rx_reg[7].CLK
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clk => rx_rdy~reg0.CLK
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clk => rx_cnt[0].CLK
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clk => rx_cnt[1].CLK
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clk => rx_cnt[2].CLK
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clk => rx_cnt[3].CLK
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clk => count[0].CLK
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clk => count[1].CLK
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clk => count[2].CLK
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clk => count[3].CLK
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clk => count[4].CLK
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clk => count[5].CLK
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clk => rx_state~5.DATAIN
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rst_n => rx_data[0]~reg0.ACLR
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rst_n => rx_data[1]~reg0.ACLR
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rst_n => rx_data[2]~reg0.ACLR
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rst_n => rx_data[3]~reg0.ACLR
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rst_n => rx_data[4]~reg0.ACLR
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rst_n => rx_data[5]~reg0.ACLR
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rst_n => rx_data[6]~reg0.ACLR
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rst_n => rx_data[7]~reg0.ACLR
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rst_n => rx_reg[0].ACLR
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rst_n => rx_reg[1].ACLR
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rst_n => rx_reg[2].ACLR
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rst_n => rx_reg[3].ACLR
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rst_n => rx_reg[4].ACLR
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rst_n => rx_reg[5].ACLR
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rst_n => rx_reg[6].ACLR
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rst_n => rx_reg[7].ACLR
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rst_n => rx_rdy~reg0.ACLR
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rst_n => rx_cnt[0].ACLR
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rst_n => rx_cnt[1].ACLR
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rst_n => rx_cnt[2].ACLR
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rst_n => rx_cnt[3].ACLR
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rst_n => count[0].ACLR
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rst_n => count[1].ACLR
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rst_n => count[2].ACLR
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rst_n => count[3].ACLR
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rst_n => count[4].ACLR
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rst_n => count[5].ACLR
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rst_n => rx_state~7.DATAIN
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rx_en => count.OUTPUTSELECT
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rx_en => count.OUTPUTSELECT
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rx_en => count.OUTPUTSELECT
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rx_en => count.OUTPUTSELECT
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rx_en => count.OUTPUTSELECT
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rx_en => count.OUTPUTSELECT
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rx_en => rx_state.OUTPUTSELECT
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rx_en => rx_state.OUTPUTSELECT
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rx_en => rx_state.OUTPUTSELECT
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rx_en => rx_state.OUTPUTSELECT
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rx_en => rx_cnt.OUTPUTSELECT
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rx_en => rx_cnt.OUTPUTSELECT
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rx_en => rx_cnt.OUTPUTSELECT
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rx_en => rx_cnt.OUTPUTSELECT
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rx_en => rx_rdy.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_reg.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_en => rx_data.OUTPUTSELECT
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_reg.DATAB
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rx_pin => rx_state.OUTPUTSELECT
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rx_pin => rx_state.OUTPUTSELECT
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rx_pin => rx_state.OUTPUTSELECT
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rx_pin => rx_state.OUTPUTSELECT
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rx_pin => count.OUTPUTSELECT
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rx_pin => count.OUTPUTSELECT
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rx_pin => count.OUTPUTSELECT
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rx_pin => count.OUTPUTSELECT
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rx_pin => count.OUTPUTSELECT
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rx_pin => count.OUTPUTSELECT
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rx_rdy <= rx_rdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[0] <= rx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[1] <= rx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[2] <= rx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[3] <= rx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[4] <= rx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[5] <= rx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[6] <= rx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[7] <= rx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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