150 lines
3.7 KiB
Verilog
150 lines
3.7 KiB
Verilog
module uart_top(
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input wire clk,
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input wire rst_n,
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output wire clk_uart_tx,
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output wire tx_pin,
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output wire tx_busy,
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input wire rx_pin,
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output wire[7:0] rx_data,
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output wire rx_rdy
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);
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// assign clk_uart_tx = clk;
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div_clk #(
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.COUNT_WITH (6),
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.DIV (6'd50)
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)
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uart_div_c0(
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.clk(clk),
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.rst_n(rst_n),
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.clk_div(clk_uart_tx)
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);
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reg send_flag;
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reg[7:0] send_data;
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reg send_state;
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parameter SEND_IDLE = 1'd0;
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parameter SEND_START = 1'd1;
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reg[1:0] rx_rdy_state;
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reg[1:0] tx_busy_state;
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always (posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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send_state <= SEND_IDLE;
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end
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else begin
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rx_rdy_state[0] <= rx_rdy;
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rx_rdy_state[1] <= rx_rdy_state[0];
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rx_rdy <= rx_rdy_state[1];
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tx_busy_state[0] <= tx_busy;
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case(send_state)
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SEND_IDLE: begin
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if(rx_rdy_state[1]==1'b0 && rx_rdy_state[0]==1'b1) begin
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send_state <= SEND_START;
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end
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end
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SEND_START: begin
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end
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default:send_state <= send_state;
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endcase
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end
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end
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uart_tx uart_tx_c0(
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.clk(clk_uart_tx),
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.rst_n(rst_n),
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.tx_en(1'b1),
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.tx_start(send_flag),
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.tx_data(send_data),
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.tx_busy(tx_busy),
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.tx_out(tx_pin)
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);
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uart_rx uart_rx_c0(
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.clk(clk_uart_tx),
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.rst_n(rst_n),
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.rx_en(1'b1),
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.rx_data(rx_data),
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.rx_rdy(rx_rdy),
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.rx(rx_pin)
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);
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// reg [1:0] uart_send_state;
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// reg [1:0] uart_send_next_state;
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// parameter UART_OFF = 2'd0;
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// parameter UART_SEND = 2'd1;
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// parameter UART_WAIT = 2'd2;
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// always @ (posedge clk or negedge rst_n) begin
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// if(~rst_n) begin
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// uart_send_state <= UART_OFF;
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// end else begin
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// uart_send_state <= uart_send_next_state;
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// end
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// end
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// always@(*) begin
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// case(uart_send_state)
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// UART_OFF: begin
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// uart_send_next_state <= UART_SEND;
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// end
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// UART_SEND: begin
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// if(tx_busy == 1'd1) begin
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// uart_send_next_state <= UART_WAIT;
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// end
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// else begin
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// uart_send_next_state <= UART_SEND;
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// end
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// end
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// UART_WAIT: begin
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// if(tx_busy == 1'd0) begin
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// uart_send_next_state <= UART_SEND;
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// end
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// else begin
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// uart_send_next_state <= UART_WAIT;
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// end
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// end
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// default : uart_send_next_state <= uart_send_next_state;
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// endcase
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// end
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// always @( *) begin
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// case(uart_send_state)
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// UART_OFF: tx_en <= 1'b0;
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// UART_SEND: tx_en <= 1'b1;
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// UART_WAIT: tx_en <= 1'b1;
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// default : tx_en <= 1'b1;
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// endcase
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// end
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// always @(posedge clk or negedge rst_n) begin
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// if(~rst_n) begin
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// tx_start <= 1'b0;
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// tx_data <= 8'b0;
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// end
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// else begin
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// case(uart_send_state)
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// UART_OFF: begin
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// tx_start <= 1'b0;
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// tx_data <= 8'b0;
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// end
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// UART_SEND:begin
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// if(tx_start == 1'b0) begin
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// tx_start <= 1'b1;
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// tx_data <= tx_data + 1'b1;
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// end
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// else begin
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// tx_start <= 1'b1;
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// tx_data <= tx_data;
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// end
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// end
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// UART_WAIT: begin
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// tx_start <= 1'b0;
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// tx_data <= tx_data;
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// end
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// default: begin
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// tx_start <= 1'b0;
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// tx_data <= tx_data;
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// end
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// endcase
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// end
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// end
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endmodule |