93 lines
2.2 KiB
Verilog
93 lines
2.2 KiB
Verilog
module uart_rx(
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input wire clk,
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input wire rst_n,
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input wire rx_en,
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input wire rx,
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output reg rx_rdy,
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output reg [7:0] rx_data
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);
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reg [7:0] rx_reg;
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reg [3:0] rx_cnt;
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reg [1:0] state;
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parameter STOP = 2'd0, IDLE = 2'd1, DATA = 2'd2;
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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state <= IDLE;
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end
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else begin
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if(rx_en==1'b0) begin
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state <= STOP;
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end
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else begin
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case(state)
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STOP: begin
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state <= IDLE;
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end
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IDLE: begin
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if(rx==1'b0) begin
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state <= DATA;
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end
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else begin
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state <= IDLE;
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end
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end
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DATA: begin
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if(rx_cnt==4'd8) begin
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state <= IDLE;
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end
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else begin
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state <= DATA;
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end
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end
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default: begin
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state <= state;
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end
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endcase
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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rx_cnt <= 4'd0;
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rx_reg <= 8'd0;
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rx_data <= 8'd0;
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rx_rdy <= 1'b0;
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end
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else begin
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case(state)
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IDLE: begin
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rx_cnt <= 4'd0;
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rx_reg <= 8'd0;
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rx_data <= rx_data;
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rx_rdy <= 1'b0;
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end
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DATA: begin
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if(rx_cnt<4'd8) begin
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rx_reg[rx_cnt] <= rx;
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rx_cnt <= rx_cnt + 1'b1;
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end
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else begin
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rx_reg <= rx_reg;
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rx_cnt <= rx_cnt;
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end
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if(rx_cnt==4'd8) begin
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rx_data <= rx_reg;
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rx_rdy <= 1'b1;
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end
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else begin
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rx_data <= rx_data;
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rx_rdy <= 1'b0;
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end
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end
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default : begin
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rx_reg <= rx_reg;
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rx_cnt <= rx_cnt;
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rx_data <= rx_data;
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rx_rdy <= rx_rdy;
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end
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endcase
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end
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end
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endmodule |