FPGA_module/uart/par/output_files/Chain1.cdf

14 lines
320 B
Mathematica

/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP4CE10F17) Path("E:/FPGA/FPGA_lib/uart/par/output_files/") File("excute.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;