12 lines
4.9 KiB
Plaintext
12 lines
4.9 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1722739188304 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722739188304 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 04 10:39:48 2024 " "Processing started: Sun Aug 04 10:39:48 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722739188304 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1722739188304 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off excute -c excute " "Command: quartus_map --read_settings_files=on --write_settings_files=off excute -c excute" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1722739188304 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1722739188643 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/uart/uart_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/uart/uart_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" { } { { "../uart_rx.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_rx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722739188683 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722739188683 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/uart/div_clk.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/uart/div_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_clk " "Found entity 1: div_clk" { } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/uart/div_clk.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722739188685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722739188685 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/uart/uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/uart/uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "../uart_tx.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_tx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722739188686 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722739188686 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"(\"; expecting \"@\", or an identifier uart_top.v(27) " "Verilog HDL syntax error at uart_top.v(27) near text \"(\"; expecting \"@\", or an identifier" { } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1722739188687 ""}
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{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "uart_top uart_top.v(1) " "Ignored design unit \"uart_top\" at uart_top.v(1) due to previous errors" { } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1722739188688 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/uart/uart_top.v 0 0 " "Found 0 design units, including 0 entities, in source file /fpga/fpga_lib/uart/uart_top.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722739188688 ""}
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{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4604 " "Peak virtual memory: 4604 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722739189738 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 04 10:39:49 2024 " "Processing ended: Sun Aug 04 10:39:49 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722739189738 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722739189738 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722739189738 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1722739189738 ""}
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