136 lines
3.5 KiB
Plaintext
136 lines
3.5 KiB
Plaintext
|uart_top
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clk => clk.IN1
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rst_n => rst_n.IN3
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clk_uart_tx <= clk_uart_tx.DB_MAX_OUTPUT_PORT_TYPE
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tx_pin <= uart_tx:uart_tx_c0.tx_out
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tx_busy <= uart_tx:uart_tx_c0.tx_busy
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rx_pin => rx_pin.IN1
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rx_data[0] <= uart_rx:uart_rx_c0.rx_data
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rx_data[1] <= uart_rx:uart_rx_c0.rx_data
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rx_data[2] <= uart_rx:uart_rx_c0.rx_data
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rx_data[3] <= uart_rx:uart_rx_c0.rx_data
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rx_data[4] <= uart_rx:uart_rx_c0.rx_data
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rx_data[5] <= uart_rx:uart_rx_c0.rx_data
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rx_data[6] <= uart_rx:uart_rx_c0.rx_data
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rx_data[7] <= uart_rx:uart_rx_c0.rx_data
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rx_rdy <= uart_rx:uart_rx_c0.rx_rdy
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|uart_top|div_clk:uart_div_c0
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clk => clk_div~reg0.CLK
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clk => count[0].CLK
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clk => count[1].CLK
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clk => count[2].CLK
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clk => count[3].CLK
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clk => count[4].CLK
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clk => count[5].CLK
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rst_n => clk_div~reg0.ACLR
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rst_n => count[0].ACLR
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rst_n => count[1].ACLR
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rst_n => count[2].ACLR
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rst_n => count[3].ACLR
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rst_n => count[4].ACLR
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rst_n => count[5].ACLR
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clk_div <= clk_div~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|uart_top|uart_tx:uart_tx_c0
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clk => cnt[0].CLK
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clk => cnt[1].CLK
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clk => cnt[2].CLK
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clk => cnt[3].CLK
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clk => tx_out~reg0.CLK
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clk => state~1.DATAIN
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rst_n => cnt[0].ACLR
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rst_n => cnt[1].ACLR
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rst_n => cnt[2].ACLR
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rst_n => cnt[3].ACLR
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rst_n => tx_out~reg0.PRESET
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rst_n => state~3.DATAIN
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tx_en => state.OUTPUTSELECT
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tx_en => state.OUTPUTSELECT
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tx_en => state.STA_OFF.DATAIN
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tx_start => Selector2.IN2
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tx_start => Selector1.IN1
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tx_data[0] => Selector5.IN2
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tx_data[1] => Selector3.IN2
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tx_data[2] => Selector0.IN2
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tx_data[3] => Selector6.IN2
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tx_data[4] => Selector7.IN2
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tx_data[5] => Selector8.IN2
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tx_data[6] => Selector9.IN2
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tx_data[7] => Selector10.IN2
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tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
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tx_out <= tx_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|uart_top|uart_rx:uart_rx_c0
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clk => rx_rdy~reg0.CLK
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clk => rx_data[0]~reg0.CLK
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clk => rx_data[1]~reg0.CLK
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clk => rx_data[2]~reg0.CLK
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clk => rx_data[3]~reg0.CLK
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clk => rx_data[4]~reg0.CLK
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clk => rx_data[5]~reg0.CLK
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clk => rx_data[6]~reg0.CLK
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clk => rx_data[7]~reg0.CLK
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clk => rx_reg[0].CLK
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clk => rx_reg[1].CLK
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clk => rx_reg[2].CLK
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clk => rx_reg[3].CLK
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clk => rx_reg[4].CLK
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clk => rx_reg[5].CLK
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clk => rx_reg[6].CLK
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clk => rx_reg[7].CLK
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clk => rx_cnt[0].CLK
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clk => rx_cnt[1].CLK
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clk => rx_cnt[2].CLK
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clk => rx_cnt[3].CLK
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clk => state~1.DATAIN
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rst_n => rx_rdy~reg0.ACLR
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rst_n => rx_data[0]~reg0.ACLR
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rst_n => rx_data[1]~reg0.ACLR
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rst_n => rx_data[2]~reg0.ACLR
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rst_n => rx_data[3]~reg0.ACLR
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rst_n => rx_data[4]~reg0.ACLR
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rst_n => rx_data[5]~reg0.ACLR
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rst_n => rx_data[6]~reg0.ACLR
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rst_n => rx_data[7]~reg0.ACLR
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rst_n => rx_reg[0].ACLR
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rst_n => rx_reg[1].ACLR
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rst_n => rx_reg[2].ACLR
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rst_n => rx_reg[3].ACLR
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rst_n => rx_reg[4].ACLR
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rst_n => rx_reg[5].ACLR
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rst_n => rx_reg[6].ACLR
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rst_n => rx_reg[7].ACLR
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rst_n => rx_cnt[0].ACLR
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rst_n => rx_cnt[1].ACLR
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rst_n => rx_cnt[2].ACLR
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rst_n => rx_cnt[3].ACLR
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rst_n => state~3.DATAIN
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rx_en => state.OUTPUTSELECT
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rx_en => state.OUTPUTSELECT
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rx_en => state.STOP.DATAIN
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => rx_reg.DATAB
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rx => Selector0.IN2
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rx => Selector1.IN1
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rx_rdy <= rx_rdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[0] <= rx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[1] <= rx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[2] <= rx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[3] <= rx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[4] <= rx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[5] <= rx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[6] <= rx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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rx_data[7] <= rx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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