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FPGA_module/uart
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陈逸凡 0864208bd6 1 2024-08-04 14:24:44 +08:00
..
par 1 2024-08-04 14:24:44 +08:00
build.bat 1 2024-08-04 14:24:44 +08:00
div_clk.v 1 2024-08-04 14:24:44 +08:00
div_clk.v.bak 1 2024-08-04 14:24:44 +08:00
excute.ipinfo 1 2024-08-04 14:24:44 +08:00
out 1 2024-08-04 14:24:44 +08:00
uart_rx.v 1 2024-08-04 14:24:44 +08:00
uart_rx.v.bak 1 2024-08-04 14:24:44 +08:00
uart_tb.v 1 2024-08-04 14:24:44 +08:00
uart_tb.vcd 1 2024-08-04 14:24:44 +08:00
uart_top.v 1 2024-08-04 14:24:44 +08:00
uart_top.v.bak 1 2024-08-04 14:24:44 +08:00
uart_tx.v 1 2024-08-04 14:24:44 +08:00
uart_tx.v.bak 1 2024-08-04 14:24:44 +08:00