2039 lines
263 KiB
Plaintext
2039 lines
263 KiB
Plaintext
TimeQuest Timing Analyzer report for test
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Sat Aug 03 00:24:21 2024
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Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. TimeQuest Timing Analyzer Summary
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3. Parallel Compilation
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4. Clocks
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5. Slow 1200mV 85C Model Fmax Summary
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6. Timing Closure Recommendations
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7. Slow 1200mV 85C Model Setup Summary
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8. Slow 1200mV 85C Model Hold Summary
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9. Slow 1200mV 85C Model Recovery Summary
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10. Slow 1200mV 85C Model Removal Summary
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11. Slow 1200mV 85C Model Minimum Pulse Width Summary
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12. Slow 1200mV 85C Model Setup: 'clk'
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13. Slow 1200mV 85C Model Setup: 'div_clk:div_clk_inst|clk_div'
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14. Slow 1200mV 85C Model Hold: 'clk'
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15. Slow 1200mV 85C Model Hold: 'div_clk:div_clk_inst|clk_div'
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16. Slow 1200mV 85C Model Minimum Pulse Width: 'clk'
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17. Slow 1200mV 85C Model Minimum Pulse Width: 'div_clk:div_clk_inst|clk_div'
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18. Clock to Output Times
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19. Minimum Clock to Output Times
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20. Slow 1200mV 85C Model Metastability Report
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21. Slow 1200mV 0C Model Fmax Summary
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22. Slow 1200mV 0C Model Setup Summary
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23. Slow 1200mV 0C Model Hold Summary
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24. Slow 1200mV 0C Model Recovery Summary
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25. Slow 1200mV 0C Model Removal Summary
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26. Slow 1200mV 0C Model Minimum Pulse Width Summary
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27. Slow 1200mV 0C Model Setup: 'clk'
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28. Slow 1200mV 0C Model Setup: 'div_clk:div_clk_inst|clk_div'
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29. Slow 1200mV 0C Model Hold: 'clk'
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30. Slow 1200mV 0C Model Hold: 'div_clk:div_clk_inst|clk_div'
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31. Slow 1200mV 0C Model Minimum Pulse Width: 'clk'
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32. Slow 1200mV 0C Model Minimum Pulse Width: 'div_clk:div_clk_inst|clk_div'
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33. Clock to Output Times
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34. Minimum Clock to Output Times
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35. Slow 1200mV 0C Model Metastability Report
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36. Fast 1200mV 0C Model Setup Summary
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37. Fast 1200mV 0C Model Hold Summary
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38. Fast 1200mV 0C Model Recovery Summary
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39. Fast 1200mV 0C Model Removal Summary
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40. Fast 1200mV 0C Model Minimum Pulse Width Summary
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41. Fast 1200mV 0C Model Setup: 'clk'
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42. Fast 1200mV 0C Model Setup: 'div_clk:div_clk_inst|clk_div'
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43. Fast 1200mV 0C Model Hold: 'clk'
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44. Fast 1200mV 0C Model Hold: 'div_clk:div_clk_inst|clk_div'
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45. Fast 1200mV 0C Model Minimum Pulse Width: 'clk'
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46. Fast 1200mV 0C Model Minimum Pulse Width: 'div_clk:div_clk_inst|clk_div'
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47. Clock to Output Times
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48. Minimum Clock to Output Times
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49. Fast 1200mV 0C Model Metastability Report
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50. Multicorner Timing Analysis Summary
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51. Clock to Output Times
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52. Minimum Clock to Output Times
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53. Board Trace Model Assignments
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54. Input Transition Times
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55. Signal Integrity Metrics (Slow 1200mv 0c Model)
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56. Signal Integrity Metrics (Slow 1200mv 85c Model)
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57. Signal Integrity Metrics (Fast 1200mv 0c Model)
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58. Setup Transfers
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59. Hold Transfers
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60. Report TCCS
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61. Report RSKM
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62. Unconstrained Paths
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63. TimeQuest Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+--------------------------------------------------------------------------+
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; TimeQuest Timing Analyzer Summary ;
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+--------------------+-----------------------------------------------------+
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; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
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; Revision Name ; test ;
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; Device Family ; Cyclone IV E ;
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; Device Name ; EP4CE10F17C8 ;
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; Timing Models ; Final ;
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; Delay Model ; Combined ;
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; Rise/Fall Delays ; Enabled ;
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+--------------------+-----------------------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 12 ;
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; Maximum allowed ; 12 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 12 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processors 2-12 ; < 0.1% ;
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+----------------------------+-------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clocks ;
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+------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------+
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; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
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+------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------+
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; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ;
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; div_clk:div_clk_inst|clk_div ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { div_clk:div_clk_inst|clk_div } ;
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+------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------+
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+-----------------------------------------------------------------------------------------------------------------------------+
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; Slow 1200mV 85C Model Fmax Summary ;
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+------------+-----------------+------------------------------+---------------------------------------------------------------+
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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+------------+-----------------+------------------------------+---------------------------------------------------------------+
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; 336.13 MHz ; 250.0 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ;
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; 426.99 MHz ; 402.09 MHz ; div_clk:div_clk_inst|clk_div ; limit due to minimum period restriction (tmin) ;
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+------------+-----------------+------------------------------+---------------------------------------------------------------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
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----------------------------------
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; Timing Closure Recommendations ;
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----------------------------------
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HTML report is unavailable in plain text report export.
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+-------------------------------------------------------+
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; Slow 1200mV 85C Model Setup Summary ;
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+------------------------------+--------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+------------------------------+--------+---------------+
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; clk ; -1.975 ; -15.066 ;
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; div_clk:div_clk_inst|clk_div ; -1.342 ; -8.886 ;
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+------------------------------+--------+---------------+
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+------------------------------------------------------+
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; Slow 1200mV 85C Model Hold Summary ;
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+------------------------------+-------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+------------------------------+-------+---------------+
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; clk ; 0.029 ; 0.000 ;
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; div_clk:div_clk_inst|clk_div ; 0.464 ; 0.000 ;
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+------------------------------+-------+---------------+
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------------------------------------------
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; Slow 1200mV 85C Model Recovery Summary ;
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------------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1200mV 85C Model Removal Summary ;
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-----------------------------------------
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No paths to report.
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+-------------------------------------------------------+
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; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
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+------------------------------+--------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+------------------------------+--------+---------------+
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; clk ; -3.000 ; -19.357 ;
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; div_clk:div_clk_inst|clk_div ; -1.487 ; -23.792 ;
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+------------------------------+--------+---------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Slow 1200mV 85C Model Setup: 'clk' ;
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+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
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; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
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+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
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; -1.975 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.895 ;
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; -1.966 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.886 ;
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; -1.798 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.718 ;
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; -1.789 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.709 ;
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; -1.765 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.685 ;
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; -1.689 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.609 ;
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; -1.665 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.585 ;
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; -1.660 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.580 ;
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; -1.659 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.579 ;
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; -1.656 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.576 ;
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; -1.651 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.571 ;
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; -1.650 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.570 ;
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; -1.620 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.540 ;
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; -1.617 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.537 ;
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; -1.599 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.519 ;
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; -1.547 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.467 ;
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; -1.509 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.429 ;
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; -1.497 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 2.417 ;
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; -1.488 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.408 ;
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; -1.483 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.403 ;
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; -1.482 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.402 ;
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; -1.479 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.399 ;
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; -1.477 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.397 ;
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; -1.474 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 2.394 ;
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; -1.474 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.394 ;
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; -1.473 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.393 ;
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; -1.455 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.375 ;
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; -1.450 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.370 ;
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; -1.449 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.369 ;
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; -1.444 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 2.364 ;
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; -1.438 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.358 ;
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; -1.432 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.352 ;
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; -1.431 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.351 ;
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; -1.416 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.336 ;
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; -1.384 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 2.304 ;
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; -1.380 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.300 ;
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; -1.354 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.274 ;
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; -1.354 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 2.274 ;
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; -1.351 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 2.271 ;
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; -1.333 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.253 ;
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; -1.329 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 2.249 ;
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; -1.328 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.248 ;
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; -1.328 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.248 ;
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; -1.302 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.222 ;
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; -1.299 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 2.219 ;
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; -1.298 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 2.218 ;
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; -1.278 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.081 ; 2.198 ;
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; -1.238 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.158 ;
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; -1.229 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 2.149 ;
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; -1.210 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 2.130 ;
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; -1.208 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 2.128 ;
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; -1.183 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.103 ;
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; -1.178 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 2.098 ;
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; -1.153 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 2.073 ;
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; -1.148 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 2.068 ;
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; -1.141 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 2.061 ;
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; -1.140 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.060 ;
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; -1.083 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 2.003 ;
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; -1.083 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.003 ;
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; -1.065 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.081 ; 1.985 ;
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; -1.064 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 1.984 ;
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; -1.059 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.979 ;
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; -1.058 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 1.978 ;
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; -1.036 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.081 ; 1.956 ;
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; -1.035 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 1.955 ;
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; -1.032 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.952 ;
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; -1.006 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.926 ;
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; -1.005 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 1.925 ;
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; -1.002 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 1.922 ;
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; -0.946 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.081 ; 1.866 ;
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; -0.944 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 1.864 ;
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; -0.937 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.857 ;
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; -0.916 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.836 ;
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; -0.912 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 1.832 ;
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; -0.911 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 1.831 ;
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; -0.362 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[0] ; clk ; clk ; 1.000 ; -0.081 ; 1.282 ;
|
|
; -0.360 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.081 ; 1.280 ;
|
|
; -0.360 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.280 ;
|
|
; -0.352 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.081 ; 1.272 ;
|
|
; -0.338 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.258 ;
|
|
; -0.336 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.081 ; 1.256 ;
|
|
; -0.142 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.081 ; 1.062 ;
|
|
; 0.105 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 0.500 ; 2.507 ; 3.154 ;
|
|
; 0.451 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 1.000 ; 2.507 ; 3.308 ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 85C Model Setup: 'div_clk:div_clk_inst|clk_div' ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; -1.342 ; data[2] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.261 ;
|
|
; -1.251 ; data[1] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.170 ;
|
|
; -1.243 ; data[0] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.162 ;
|
|
; -1.227 ; data[0] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.146 ;
|
|
; -1.224 ; data[1] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.143 ;
|
|
; -1.196 ; data[2] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.115 ;
|
|
; -1.181 ; data[4] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.100 ;
|
|
; -1.166 ; data[2] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.085 ;
|
|
; -1.105 ; data[1] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.024 ;
|
|
; -1.098 ; data[3] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.017 ;
|
|
; -1.097 ; data[0] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.016 ;
|
|
; -1.082 ; data[3] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.001 ;
|
|
; -1.081 ; data[0] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 2.000 ;
|
|
; -1.078 ; data[1] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.997 ;
|
|
; -1.050 ; data[2] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.969 ;
|
|
; -1.047 ; data[6] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.966 ;
|
|
; -1.035 ; data[4] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.954 ;
|
|
; -1.020 ; data[2] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.939 ;
|
|
; -1.005 ; data[4] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.924 ;
|
|
; -0.959 ; data[1] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.878 ;
|
|
; -0.952 ; data[5] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.871 ;
|
|
; -0.952 ; data[3] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.871 ;
|
|
; -0.951 ; data[0] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.870 ;
|
|
; -0.936 ; data[5] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.855 ;
|
|
; -0.936 ; data[3] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.855 ;
|
|
; -0.935 ; data[0] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.854 ;
|
|
; -0.932 ; data[1] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.851 ;
|
|
; -0.375 ; data[1] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.294 ;
|
|
; -0.367 ; data[5] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.286 ;
|
|
; -0.367 ; data[3] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.286 ;
|
|
; -0.366 ; data[2] ; a4~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.080 ; 1.287 ;
|
|
; -0.366 ; data[0] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.285 ;
|
|
; -0.351 ; data[2] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.270 ;
|
|
; -0.349 ; data[6] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.268 ;
|
|
; -0.336 ; data[4] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.255 ;
|
|
; -0.334 ; data[1] ; a3~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.253 ;
|
|
; -0.329 ; data[0] ; a2~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.248 ;
|
|
; -0.327 ; data[3] ; a5~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 1.246 ;
|
|
; -0.180 ; data[5] ; a7~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.083 ; 1.098 ;
|
|
; -0.144 ; data[6] ; a8~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.083 ; 1.062 ;
|
|
; 0.013 ; data[7] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 0.906 ;
|
|
; 0.023 ; data[4] ; a6~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 0.896 ;
|
|
; 0.026 ; data[7] ; a9~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 0.893 ;
|
|
; 0.061 ; data[0] ; data[0] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.082 ; 0.858 ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 85C Model Hold: 'clk' ;
|
|
+-------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; 0.029 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 0.000 ; 2.603 ; 3.135 ;
|
|
; 0.399 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; -0.500 ; 2.603 ; 3.005 ;
|
|
; 0.686 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 0.979 ;
|
|
; 0.745 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.038 ;
|
|
; 0.746 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.039 ;
|
|
; 0.746 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.039 ;
|
|
; 0.746 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.039 ;
|
|
; 0.748 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.041 ;
|
|
; 0.764 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[0] ; clk ; clk ; 0.000 ; 0.081 ; 1.057 ;
|
|
; 1.099 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.392 ;
|
|
; 1.099 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.392 ;
|
|
; 1.100 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.393 ;
|
|
; 1.107 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.400 ;
|
|
; 1.107 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.400 ;
|
|
; 1.109 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.402 ;
|
|
; 1.116 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.409 ;
|
|
; 1.117 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.410 ;
|
|
; 1.120 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.413 ;
|
|
; 1.142 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.435 ;
|
|
; 1.145 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.438 ;
|
|
; 1.150 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.443 ;
|
|
; 1.230 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.523 ;
|
|
; 1.230 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.523 ;
|
|
; 1.231 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.524 ;
|
|
; 1.239 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.532 ;
|
|
; 1.240 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.533 ;
|
|
; 1.247 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.540 ;
|
|
; 1.248 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.541 ;
|
|
; 1.251 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.544 ;
|
|
; 1.258 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.551 ;
|
|
; 1.260 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.553 ;
|
|
; 1.370 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.663 ;
|
|
; 1.371 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.664 ;
|
|
; 1.380 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.673 ;
|
|
; 1.380 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.673 ;
|
|
; 1.389 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.682 ;
|
|
; 1.391 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.684 ;
|
|
; 1.397 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.690 ;
|
|
; 1.398 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.691 ;
|
|
; 1.469 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.762 ;
|
|
; 1.470 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.763 ;
|
|
; 1.475 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.768 ;
|
|
; 1.490 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.783 ;
|
|
; 1.500 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.793 ;
|
|
; 1.509 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.802 ;
|
|
; 1.511 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.804 ;
|
|
; 1.511 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.804 ;
|
|
; 1.515 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.808 ;
|
|
; 1.518 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.811 ;
|
|
; 1.520 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.813 ;
|
|
; 1.528 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.821 ;
|
|
; 1.529 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.822 ;
|
|
; 1.537 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.830 ;
|
|
; 1.607 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.900 ;
|
|
; 1.610 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.903 ;
|
|
; 1.628 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.921 ;
|
|
; 1.651 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.944 ;
|
|
; 1.668 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.961 ;
|
|
; 1.726 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.019 ;
|
|
; 1.748 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.041 ;
|
|
; 1.770 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.063 ;
|
|
; 1.868 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 2.161 ;
|
|
; 1.869 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.162 ;
|
|
; 1.877 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.170 ;
|
|
; 1.880 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.173 ;
|
|
; 1.899 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 2.192 ;
|
|
; 1.900 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.193 ;
|
|
; 1.905 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 2.198 ;
|
|
; 1.957 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 2.250 ;
|
|
; 1.958 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.251 ;
|
|
; 1.963 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 2.256 ;
|
|
; 1.964 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.257 ;
|
|
; 2.117 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 2.410 ;
|
|
; 2.117 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.081 ; 2.410 ;
|
|
; 2.118 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.411 ;
|
|
; 2.118 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.411 ;
|
|
; 2.118 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.081 ; 2.411 ;
|
|
; 2.123 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 2.416 ;
|
|
; 2.123 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.081 ; 2.416 ;
|
|
; 2.138 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.431 ;
|
|
; 2.158 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.451 ;
|
|
; 2.196 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.489 ;
|
|
; 2.356 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.649 ;
|
|
; 2.356 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.081 ; 2.649 ;
|
|
+-------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 85C Model Hold: 'div_clk:div_clk_inst|clk_div' ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; 0.464 ; data[0] ; data[0] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 0.758 ;
|
|
; 0.491 ; data[7] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 0.785 ;
|
|
; 0.508 ; data[7] ; a9~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 0.802 ;
|
|
; 0.508 ; data[4] ; a6~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 0.802 ;
|
|
; 0.706 ; data[6] ; a8~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.081 ; 0.999 ;
|
|
; 0.736 ; data[5] ; a7~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.081 ; 1.029 ;
|
|
; 0.746 ; data[4] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.040 ;
|
|
; 0.762 ; data[6] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.056 ;
|
|
; 0.763 ; data[2] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.057 ;
|
|
; 0.765 ; data[5] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.059 ;
|
|
; 0.765 ; data[3] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.059 ;
|
|
; 0.782 ; data[1] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.076 ;
|
|
; 0.782 ; data[0] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.076 ;
|
|
; 0.866 ; data[1] ; a3~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.160 ;
|
|
; 0.868 ; data[3] ; a5~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.162 ;
|
|
; 0.874 ; data[0] ; a2~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.168 ;
|
|
; 0.912 ; data[2] ; a4~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.084 ; 1.208 ;
|
|
; 1.100 ; data[4] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.394 ;
|
|
; 1.117 ; data[6] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.411 ;
|
|
; 1.117 ; data[2] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.411 ;
|
|
; 1.124 ; data[1] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.418 ;
|
|
; 1.125 ; data[0] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.419 ;
|
|
; 1.126 ; data[3] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.420 ;
|
|
; 1.126 ; data[5] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.420 ;
|
|
; 1.133 ; data[1] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.427 ;
|
|
; 1.134 ; data[0] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.428 ;
|
|
; 1.135 ; data[3] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.429 ;
|
|
; 1.135 ; data[5] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.429 ;
|
|
; 1.231 ; data[4] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.525 ;
|
|
; 1.240 ; data[4] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.534 ;
|
|
; 1.248 ; data[2] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.542 ;
|
|
; 1.257 ; data[2] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.551 ;
|
|
; 1.264 ; data[1] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.558 ;
|
|
; 1.265 ; data[0] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.559 ;
|
|
; 1.266 ; data[3] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.560 ;
|
|
; 1.273 ; data[1] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.567 ;
|
|
; 1.274 ; data[0] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.568 ;
|
|
; 1.275 ; data[3] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.569 ;
|
|
; 1.388 ; data[2] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.682 ;
|
|
; 1.397 ; data[2] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.691 ;
|
|
; 1.404 ; data[1] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.698 ;
|
|
; 1.405 ; data[0] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.699 ;
|
|
; 1.413 ; data[1] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.707 ;
|
|
; 1.414 ; data[0] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.082 ; 1.708 ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk' ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; clk ; Rise ; clk ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; 0.308 ; 0.496 ; 0.188 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|clk_div|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[0]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[1]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[2]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[3]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[4]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[5]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[6]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[7]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[8]|clk ;
|
|
; 0.448 ; 0.448 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[9]|clk ;
|
|
; 0.454 ; 0.454 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~input|o ;
|
|
; 0.467 ; 0.467 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~inputclkctrl|inclk[0] ;
|
|
; 0.467 ; 0.467 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~inputclkctrl|outclk ;
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~input|i ;
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~input|i ;
|
|
; 0.532 ; 0.532 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~inputclkctrl|inclk[0] ;
|
|
; 0.532 ; 0.532 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~inputclkctrl|outclk ;
|
|
; 0.546 ; 0.546 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~input|o ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|clk_div|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[0]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[1]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[2]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[3]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[4]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[5]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[6]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[7]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[8]|clk ;
|
|
; 0.552 ; 0.552 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[9]|clk ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 85C Model Minimum Pulse Width: 'div_clk:div_clk_inst|clk_div' ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; 0.285 ; 0.505 ; 0.220 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; 0.305 ; 0.493 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6]|clk ;
|
|
; 0.444 ; 0.444 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0|clk ;
|
|
; 0.466 ; 0.466 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|inclk[0] ;
|
|
; 0.466 ; 0.466 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|outclk ;
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div|q ;
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div|q ;
|
|
; 0.532 ; 0.532 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|inclk[0] ;
|
|
; 0.532 ; 0.532 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|outclk ;
|
|
; 0.551 ; 0.551 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7]|clk ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 6.813 ; 6.674 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 7.120 ; 6.921 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 6.842 ; 6.691 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 6.784 ; 6.649 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 6.552 ; 6.455 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 6.501 ; 6.407 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 7.149 ; 6.967 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 7.209 ; 7.015 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Minimum Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 6.552 ; 6.416 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 6.846 ; 6.653 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 6.579 ; 6.432 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 6.524 ; 6.391 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 6.300 ; 6.205 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 6.251 ; 6.158 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 6.873 ; 6.696 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 6.931 ; 6.743 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
----------------------------------------------
|
|
; Slow 1200mV 85C Model Metastability Report ;
|
|
----------------------------------------------
|
|
No synchronizer chains to report.
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Fmax Summary ;
|
|
+------------+-----------------+------------------------------+---------------------------------------------------------------+
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
|
+------------+-----------------+------------------------------+---------------------------------------------------------------+
|
|
; 361.14 MHz ; 250.0 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ;
|
|
; 477.33 MHz ; 402.09 MHz ; div_clk:div_clk_inst|clk_div ; limit due to minimum period restriction (tmin) ;
|
|
+------------+-----------------+------------------------------+---------------------------------------------------------------+
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
|
|
|
|
|
+-------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Setup Summary ;
|
|
+------------------------------+--------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------------+--------+---------------+
|
|
; clk ; -1.769 ; -12.679 ;
|
|
; div_clk:div_clk_inst|clk_div ; -1.095 ; -6.926 ;
|
|
+------------------------------+--------+---------------+
|
|
|
|
|
|
+------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Hold Summary ;
|
|
+------------------------------+-------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------------+-------+---------------+
|
|
; clk ; 0.114 ; 0.000 ;
|
|
; div_clk:div_clk_inst|clk_div ; 0.416 ; 0.000 ;
|
|
+------------------------------+-------+---------------+
|
|
|
|
|
|
-----------------------------------------
|
|
; Slow 1200mV 0C Model Recovery Summary ;
|
|
-----------------------------------------
|
|
No paths to report.
|
|
|
|
|
|
----------------------------------------
|
|
; Slow 1200mV 0C Model Removal Summary ;
|
|
----------------------------------------
|
|
No paths to report.
|
|
|
|
|
|
+-------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
|
|
+------------------------------+--------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------------+--------+---------------+
|
|
; clk ; -3.000 ; -19.357 ;
|
|
; div_clk:div_clk_inst|clk_div ; -1.487 ; -23.792 ;
|
|
+------------------------------+--------+---------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Setup: 'clk' ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; -1.769 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.699 ;
|
|
; -1.761 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.691 ;
|
|
; -1.606 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.536 ;
|
|
; -1.602 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.532 ;
|
|
; -1.593 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.523 ;
|
|
; -1.545 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.475 ;
|
|
; -1.456 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.386 ;
|
|
; -1.445 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.375 ;
|
|
; -1.440 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.370 ;
|
|
; -1.439 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.369 ;
|
|
; -1.437 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.367 ;
|
|
; -1.432 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.362 ;
|
|
; -1.431 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.361 ;
|
|
; -1.390 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.320 ;
|
|
; -1.351 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.281 ;
|
|
; -1.288 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.218 ;
|
|
; -1.282 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.212 ;
|
|
; -1.278 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.208 ;
|
|
; -1.277 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.207 ;
|
|
; -1.276 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.206 ;
|
|
; -1.276 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.206 ;
|
|
; -1.273 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.203 ;
|
|
; -1.272 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.202 ;
|
|
; -1.271 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.201 ;
|
|
; -1.269 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.199 ;
|
|
; -1.268 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.198 ;
|
|
; -1.264 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.194 ;
|
|
; -1.263 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.193 ;
|
|
; -1.248 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 2.178 ;
|
|
; -1.221 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.151 ;
|
|
; -1.216 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.146 ;
|
|
; -1.215 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.145 ;
|
|
; -1.212 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.142 ;
|
|
; -1.207 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 2.137 ;
|
|
; -1.168 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 2.098 ;
|
|
; -1.152 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.072 ; 2.082 ;
|
|
; -1.142 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.072 ; 2.072 ;
|
|
; -1.138 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.068 ;
|
|
; -1.135 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 2.065 ;
|
|
; -1.127 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 2.057 ;
|
|
; -1.127 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 2.057 ;
|
|
; -1.126 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 2.056 ;
|
|
; -1.122 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 2.052 ;
|
|
; -1.082 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 2.012 ;
|
|
; -1.081 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 2.011 ;
|
|
; -1.043 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 1.973 ;
|
|
; -1.042 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.972 ;
|
|
; -1.001 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.931 ;
|
|
; -1.000 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 1.930 ;
|
|
; -1.000 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.930 ;
|
|
; -0.991 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 1.921 ;
|
|
; -0.959 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 1.889 ;
|
|
; -0.958 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.072 ; 1.888 ;
|
|
; -0.956 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.886 ;
|
|
; -0.952 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 1.882 ;
|
|
; -0.917 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.847 ;
|
|
; -0.913 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 1.843 ;
|
|
; -0.883 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.072 ; 1.813 ;
|
|
; -0.874 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.804 ;
|
|
; -0.870 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.800 ;
|
|
; -0.869 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 1.799 ;
|
|
; -0.866 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 1.796 ;
|
|
; -0.865 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.795 ;
|
|
; -0.829 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.072 ; 1.759 ;
|
|
; -0.828 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 1.758 ;
|
|
; -0.826 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.756 ;
|
|
; -0.790 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.720 ;
|
|
; -0.789 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 1.719 ;
|
|
; -0.787 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.717 ;
|
|
; -0.749 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.072 ; 1.679 ;
|
|
; -0.748 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.678 ;
|
|
; -0.745 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 1.675 ;
|
|
; -0.743 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 1.673 ;
|
|
; -0.743 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.673 ;
|
|
; -0.740 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.670 ;
|
|
; -0.229 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[0] ; clk ; clk ; 1.000 ; -0.072 ; 1.159 ;
|
|
; -0.226 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.072 ; 1.156 ;
|
|
; -0.225 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.155 ;
|
|
; -0.219 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.072 ; 1.149 ;
|
|
; -0.207 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.137 ;
|
|
; -0.205 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.072 ; 1.135 ;
|
|
; -0.060 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.072 ; 0.990 ;
|
|
; 0.198 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 0.500 ; 2.306 ; 2.840 ;
|
|
; 0.377 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 1.000 ; 2.306 ; 3.161 ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Setup: 'div_clk:div_clk_inst|clk_div' ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; -1.095 ; data[2] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 2.024 ;
|
|
; -1.015 ; data[0] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.944 ;
|
|
; -1.011 ; data[1] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.940 ;
|
|
; -1.010 ; data[1] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.939 ;
|
|
; -1.004 ; data[0] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.933 ;
|
|
; -0.969 ; data[2] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.898 ;
|
|
; -0.956 ; data[4] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.885 ;
|
|
; -0.930 ; data[2] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.859 ;
|
|
; -0.889 ; data[0] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.818 ;
|
|
; -0.889 ; data[3] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.818 ;
|
|
; -0.885 ; data[1] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.814 ;
|
|
; -0.884 ; data[1] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.813 ;
|
|
; -0.879 ; data[3] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.808 ;
|
|
; -0.878 ; data[0] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.807 ;
|
|
; -0.843 ; data[2] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.772 ;
|
|
; -0.839 ; data[6] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.768 ;
|
|
; -0.830 ; data[4] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.759 ;
|
|
; -0.804 ; data[2] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.733 ;
|
|
; -0.791 ; data[4] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.720 ;
|
|
; -0.763 ; data[0] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.692 ;
|
|
; -0.763 ; data[5] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.692 ;
|
|
; -0.763 ; data[3] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.692 ;
|
|
; -0.759 ; data[1] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.688 ;
|
|
; -0.758 ; data[1] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.687 ;
|
|
; -0.753 ; data[5] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.682 ;
|
|
; -0.753 ; data[3] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.682 ;
|
|
; -0.752 ; data[0] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.681 ;
|
|
; -0.268 ; data[2] ; a4~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.072 ; 1.198 ;
|
|
; -0.239 ; data[1] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.168 ;
|
|
; -0.233 ; data[5] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.162 ;
|
|
; -0.233 ; data[3] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.162 ;
|
|
; -0.232 ; data[0] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.161 ;
|
|
; -0.224 ; data[0] ; a2~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.153 ;
|
|
; -0.220 ; data[3] ; a5~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.149 ;
|
|
; -0.220 ; data[2] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.149 ;
|
|
; -0.218 ; data[6] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.147 ;
|
|
; -0.216 ; data[1] ; a3~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.145 ;
|
|
; -0.207 ; data[4] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.136 ;
|
|
; -0.111 ; data[5] ; a7~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.040 ;
|
|
; -0.074 ; data[6] ; a8~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 1.003 ;
|
|
; 0.105 ; data[7] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 0.824 ;
|
|
; 0.122 ; data[4] ; a6~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 0.807 ;
|
|
; 0.124 ; data[7] ; a9~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 0.805 ;
|
|
; 0.159 ; data[0] ; data[0] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.073 ; 0.770 ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Hold: 'clk' ;
|
|
+-------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; 0.114 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 0.000 ; 2.391 ; 2.970 ;
|
|
; 0.344 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; -0.500 ; 2.391 ; 2.700 ;
|
|
; 0.618 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 0.885 ;
|
|
; 0.694 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 0.961 ;
|
|
; 0.694 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 0.961 ;
|
|
; 0.695 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 0.962 ;
|
|
; 0.696 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.072 ; 0.963 ;
|
|
; 0.699 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.072 ; 0.966 ;
|
|
; 0.717 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[0] ; clk ; clk ; 0.000 ; 0.072 ; 0.984 ;
|
|
; 1.013 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.280 ;
|
|
; 1.013 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.280 ;
|
|
; 1.015 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.282 ;
|
|
; 1.018 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.072 ; 1.285 ;
|
|
; 1.019 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.286 ;
|
|
; 1.020 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.072 ; 1.287 ;
|
|
; 1.028 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.295 ;
|
|
; 1.030 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.072 ; 1.297 ;
|
|
; 1.033 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.300 ;
|
|
; 1.057 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.324 ;
|
|
; 1.064 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.331 ;
|
|
; 1.066 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.333 ;
|
|
; 1.112 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.379 ;
|
|
; 1.116 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.383 ;
|
|
; 1.117 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.072 ; 1.384 ;
|
|
; 1.135 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.402 ;
|
|
; 1.137 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.404 ;
|
|
; 1.137 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.072 ; 1.404 ;
|
|
; 1.140 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.407 ;
|
|
; 1.142 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.409 ;
|
|
; 1.155 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.422 ;
|
|
; 1.155 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.422 ;
|
|
; 1.234 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.501 ;
|
|
; 1.239 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.506 ;
|
|
; 1.262 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.529 ;
|
|
; 1.262 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.529 ;
|
|
; 1.264 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.531 ;
|
|
; 1.264 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.531 ;
|
|
; 1.274 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.541 ;
|
|
; 1.277 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.544 ;
|
|
; 1.356 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.623 ;
|
|
; 1.359 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.626 ;
|
|
; 1.361 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.628 ;
|
|
; 1.361 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.628 ;
|
|
; 1.370 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.637 ;
|
|
; 1.377 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.644 ;
|
|
; 1.379 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.646 ;
|
|
; 1.380 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.647 ;
|
|
; 1.381 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.648 ;
|
|
; 1.384 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.651 ;
|
|
; 1.386 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.653 ;
|
|
; 1.387 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.654 ;
|
|
; 1.392 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.659 ;
|
|
; 1.396 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.072 ; 1.663 ;
|
|
; 1.468 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.735 ;
|
|
; 1.470 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.737 ;
|
|
; 1.481 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.748 ;
|
|
; 1.483 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.750 ;
|
|
; 1.503 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.072 ; 1.770 ;
|
|
; 1.569 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.836 ;
|
|
; 1.579 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 1.846 ;
|
|
; 1.589 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 1.856 ;
|
|
; 1.677 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 1.944 ;
|
|
; 1.711 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.978 ;
|
|
; 1.719 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.986 ;
|
|
; 1.721 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.988 ;
|
|
; 1.730 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.997 ;
|
|
; 1.732 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.999 ;
|
|
; 1.737 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 2.004 ;
|
|
; 1.776 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.043 ;
|
|
; 1.801 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 2.068 ;
|
|
; 1.803 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 2.070 ;
|
|
; 1.808 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 2.075 ;
|
|
; 1.918 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.185 ;
|
|
; 1.928 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.195 ;
|
|
; 1.937 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 2.204 ;
|
|
; 1.937 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.072 ; 2.204 ;
|
|
; 1.939 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.206 ;
|
|
; 1.939 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 2.206 ;
|
|
; 1.939 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.072 ; 2.206 ;
|
|
; 1.944 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 2.211 ;
|
|
; 1.944 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.072 ; 2.211 ;
|
|
; 2.010 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.277 ;
|
|
; 2.146 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.413 ;
|
|
; 2.146 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.072 ; 2.413 ;
|
|
+-------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Hold: 'div_clk:div_clk_inst|clk_div' ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; 0.416 ; data[0] ; data[0] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.684 ;
|
|
; 0.455 ; data[7] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.723 ;
|
|
; 0.476 ; data[7] ; a9~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.744 ;
|
|
; 0.478 ; data[4] ; a6~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.746 ;
|
|
; 0.628 ; data[6] ; a8~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.072 ; 0.895 ;
|
|
; 0.652 ; data[5] ; a7~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.072 ; 0.919 ;
|
|
; 0.694 ; data[4] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.962 ;
|
|
; 0.706 ; data[6] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.974 ;
|
|
; 0.709 ; data[2] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.977 ;
|
|
; 0.712 ; data[5] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.980 ;
|
|
; 0.712 ; data[3] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.980 ;
|
|
; 0.730 ; data[0] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.998 ;
|
|
; 0.731 ; data[1] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 0.999 ;
|
|
; 0.794 ; data[3] ; a5~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.062 ;
|
|
; 0.795 ; data[0] ; a2~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.063 ;
|
|
; 0.801 ; data[1] ; a3~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.069 ;
|
|
; 0.829 ; data[2] ; a4~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.097 ;
|
|
; 1.018 ; data[4] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.286 ;
|
|
; 1.027 ; data[1] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.295 ;
|
|
; 1.028 ; data[6] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.296 ;
|
|
; 1.029 ; data[0] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.297 ;
|
|
; 1.030 ; data[3] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.298 ;
|
|
; 1.030 ; data[5] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.298 ;
|
|
; 1.033 ; data[2] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.301 ;
|
|
; 1.042 ; data[1] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.310 ;
|
|
; 1.045 ; data[0] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.313 ;
|
|
; 1.046 ; data[3] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.314 ;
|
|
; 1.046 ; data[5] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.314 ;
|
|
; 1.115 ; data[4] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.383 ;
|
|
; 1.128 ; data[2] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.396 ;
|
|
; 1.140 ; data[4] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.408 ;
|
|
; 1.149 ; data[1] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.417 ;
|
|
; 1.151 ; data[0] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.419 ;
|
|
; 1.152 ; data[3] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.420 ;
|
|
; 1.155 ; data[2] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.423 ;
|
|
; 1.164 ; data[1] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.432 ;
|
|
; 1.167 ; data[0] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.435 ;
|
|
; 1.168 ; data[3] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.436 ;
|
|
; 1.250 ; data[2] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.518 ;
|
|
; 1.271 ; data[1] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.539 ;
|
|
; 1.273 ; data[0] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.541 ;
|
|
; 1.277 ; data[2] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.545 ;
|
|
; 1.286 ; data[1] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.554 ;
|
|
; 1.289 ; data[0] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.073 ; 1.557 ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk' ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; clk ; Rise ; clk ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; 0.274 ; 0.490 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; 0.324 ; 0.508 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|clk_div|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[0]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[1]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[2]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[3]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[4]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[5]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[6]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[7]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[8]|clk ;
|
|
; 0.456 ; 0.456 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[9]|clk ;
|
|
; 0.475 ; 0.475 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~input|o ;
|
|
; 0.479 ; 0.479 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~inputclkctrl|inclk[0] ;
|
|
; 0.479 ; 0.479 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~inputclkctrl|outclk ;
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~input|i ;
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~input|i ;
|
|
; 0.521 ; 0.521 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~inputclkctrl|inclk[0] ;
|
|
; 0.521 ; 0.521 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~inputclkctrl|outclk ;
|
|
; 0.525 ; 0.525 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~input|o ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|clk_div|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[0]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[1]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[2]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[3]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[4]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[5]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[6]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[7]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[8]|clk ;
|
|
; 0.543 ; 0.543 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[9]|clk ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Slow 1200mV 0C Model Minimum Pulse Width: 'div_clk:div_clk_inst|clk_div' ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; 0.270 ; 0.486 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.271 ; 0.487 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; 0.327 ; 0.511 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.328 ; 0.512 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; 0.328 ; 0.512 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; 0.459 ; 0.459 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6]|clk ;
|
|
; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7]|clk ;
|
|
; 0.481 ; 0.481 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|inclk[0] ;
|
|
; 0.481 ; 0.481 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|outclk ;
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div|q ;
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div|q ;
|
|
; 0.519 ; 0.519 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|inclk[0] ;
|
|
; 0.519 ; 0.519 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|outclk ;
|
|
; 0.539 ; 0.539 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0|clk ;
|
|
; 0.539 ; 0.539 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6]|clk ;
|
|
; 0.540 ; 0.540 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7]|clk ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 6.209 ; 6.001 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 6.503 ; 6.216 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 6.229 ; 6.013 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 6.177 ; 5.976 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 5.945 ; 5.807 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 5.894 ; 5.761 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 6.518 ; 6.261 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 6.573 ; 6.304 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Minimum Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 5.948 ; 5.747 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 6.230 ; 5.953 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 5.968 ; 5.759 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 5.917 ; 5.722 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 5.694 ; 5.560 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 5.646 ; 5.517 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 6.244 ; 5.996 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 6.297 ; 6.037 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
---------------------------------------------
|
|
; Slow 1200mV 0C Model Metastability Report ;
|
|
---------------------------------------------
|
|
No synchronizer chains to report.
|
|
|
|
|
|
+-------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Setup Summary ;
|
|
+------------------------------+--------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------------+--------+---------------+
|
|
; clk ; -0.231 ; -0.813 ;
|
|
; div_clk:div_clk_inst|clk_div ; -0.022 ; -0.022 ;
|
|
+------------------------------+--------+---------------+
|
|
|
|
|
|
+-------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Hold Summary ;
|
|
+------------------------------+--------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------------+--------+---------------+
|
|
; clk ; -0.129 ; -0.129 ;
|
|
; div_clk:div_clk_inst|clk_div ; 0.193 ; 0.000 ;
|
|
+------------------------------+--------+---------------+
|
|
|
|
|
|
-----------------------------------------
|
|
; Fast 1200mV 0C Model Recovery Summary ;
|
|
-----------------------------------------
|
|
No paths to report.
|
|
|
|
|
|
----------------------------------------
|
|
; Fast 1200mV 0C Model Removal Summary ;
|
|
----------------------------------------
|
|
No paths to report.
|
|
|
|
|
|
+-------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
|
|
+------------------------------+--------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------------+--------+---------------+
|
|
; clk ; -3.000 ; -14.715 ;
|
|
; div_clk:div_clk_inst|clk_div ; -1.000 ; -16.000 ;
|
|
+------------------------------+--------+---------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Setup: 'clk' ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; -0.231 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.181 ;
|
|
; -0.225 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.175 ;
|
|
; -0.169 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.119 ;
|
|
; -0.158 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.108 ;
|
|
; -0.154 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.104 ;
|
|
; -0.136 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.086 ;
|
|
; -0.126 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.076 ;
|
|
; -0.125 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.075 ;
|
|
; -0.124 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.074 ;
|
|
; -0.122 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 1.072 ;
|
|
; -0.122 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 1.072 ;
|
|
; -0.121 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 1.071 ;
|
|
; -0.119 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 1.069 ;
|
|
; -0.118 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 1.068 ;
|
|
; -0.109 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.059 ;
|
|
; -0.089 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 1.039 ;
|
|
; -0.085 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 1.035 ;
|
|
; -0.074 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 1.024 ;
|
|
; -0.074 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 1.024 ;
|
|
; -0.071 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.021 ;
|
|
; -0.067 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 1.017 ;
|
|
; -0.064 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 1.014 ;
|
|
; -0.063 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 1.013 ;
|
|
; -0.056 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.006 ;
|
|
; -0.054 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 1.004 ;
|
|
; -0.051 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 1.001 ;
|
|
; -0.048 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.998 ;
|
|
; -0.047 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.997 ;
|
|
; -0.044 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.994 ;
|
|
; -0.040 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 0.990 ;
|
|
; -0.040 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.990 ;
|
|
; -0.038 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.988 ;
|
|
; -0.037 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.987 ;
|
|
; -0.034 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.984 ;
|
|
; -0.031 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.981 ;
|
|
; -0.021 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.971 ;
|
|
; -0.021 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.971 ;
|
|
; -0.017 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.967 ;
|
|
; -0.017 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.967 ;
|
|
; -0.006 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.956 ;
|
|
; -0.006 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.956 ;
|
|
; -0.005 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.955 ;
|
|
; 0.002 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 0.948 ;
|
|
; 0.008 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 1.000 ; -0.037 ; 0.942 ;
|
|
; 0.026 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.924 ;
|
|
; 0.027 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.923 ;
|
|
; 0.031 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.919 ;
|
|
; 0.031 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.919 ;
|
|
; 0.040 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.910 ;
|
|
; 0.047 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.903 ;
|
|
; 0.048 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.902 ;
|
|
; 0.051 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.899 ;
|
|
; 0.052 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.898 ;
|
|
; 0.061 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.889 ;
|
|
; 0.062 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.888 ;
|
|
; 0.063 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.887 ;
|
|
; 0.065 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.885 ;
|
|
; 0.097 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.853 ;
|
|
; 0.099 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.851 ;
|
|
; 0.112 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.838 ;
|
|
; 0.115 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.835 ;
|
|
; 0.116 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.834 ;
|
|
; 0.116 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.834 ;
|
|
; 0.119 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.037 ; 0.831 ;
|
|
; 0.120 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.830 ;
|
|
; 0.120 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.830 ;
|
|
; 0.129 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.821 ;
|
|
; 0.130 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.820 ;
|
|
; 0.131 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.819 ;
|
|
; 0.165 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.785 ;
|
|
; 0.167 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.037 ; 0.783 ;
|
|
; 0.169 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.781 ;
|
|
; 0.199 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.751 ;
|
|
; 0.199 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.751 ;
|
|
; 0.200 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.750 ;
|
|
; 0.227 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 0.500 ; 1.136 ; 1.491 ;
|
|
; 0.402 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[0] ; clk ; clk ; 1.000 ; -0.037 ; 0.548 ;
|
|
; 0.402 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 1.000 ; -0.037 ; 0.548 ;
|
|
; 0.403 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 1.000 ; -0.037 ; 0.547 ;
|
|
; 0.404 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.546 ;
|
|
; 0.412 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.538 ;
|
|
; 0.413 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 1.000 ; -0.037 ; 0.537 ;
|
|
; 0.496 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 1.000 ; -0.037 ; 0.454 ;
|
|
; 0.873 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 1.000 ; 1.136 ; 1.345 ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Setup: 'div_clk:div_clk_inst|clk_div' ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; -0.022 ; data[2] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.972 ;
|
|
; 0.025 ; data[0] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.925 ;
|
|
; 0.027 ; data[1] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.923 ;
|
|
; 0.042 ; data[2] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.908 ;
|
|
; 0.046 ; data[2] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.904 ;
|
|
; 0.052 ; data[4] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.898 ;
|
|
; 0.055 ; data[0] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.895 ;
|
|
; 0.056 ; data[1] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.894 ;
|
|
; 0.093 ; data[0] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.857 ;
|
|
; 0.094 ; data[3] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.856 ;
|
|
; 0.095 ; data[1] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.855 ;
|
|
; 0.110 ; data[2] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.840 ;
|
|
; 0.114 ; data[2] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.836 ;
|
|
; 0.116 ; data[4] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.834 ;
|
|
; 0.118 ; data[6] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.832 ;
|
|
; 0.120 ; data[4] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.830 ;
|
|
; 0.123 ; data[0] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.827 ;
|
|
; 0.124 ; data[3] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.826 ;
|
|
; 0.124 ; data[1] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.826 ;
|
|
; 0.161 ; data[0] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.789 ;
|
|
; 0.162 ; data[5] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.788 ;
|
|
; 0.162 ; data[3] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.788 ;
|
|
; 0.163 ; data[1] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.787 ;
|
|
; 0.191 ; data[0] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.759 ;
|
|
; 0.192 ; data[5] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.758 ;
|
|
; 0.192 ; data[3] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.758 ;
|
|
; 0.192 ; data[1] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.758 ;
|
|
; 0.396 ; data[2] ; a4~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.554 ;
|
|
; 0.397 ; data[0] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.553 ;
|
|
; 0.398 ; data[5] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.552 ;
|
|
; 0.398 ; data[3] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.552 ;
|
|
; 0.398 ; data[1] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.552 ;
|
|
; 0.407 ; data[2] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.543 ;
|
|
; 0.410 ; data[6] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.540 ;
|
|
; 0.413 ; data[1] ; a3~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.537 ;
|
|
; 0.413 ; data[4] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.537 ;
|
|
; 0.417 ; data[0] ; a2~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.533 ;
|
|
; 0.418 ; data[3] ; a5~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.532 ;
|
|
; 0.476 ; data[5] ; a7~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.038 ; 0.473 ;
|
|
; 0.490 ; data[6] ; a8~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.038 ; 0.459 ;
|
|
; 0.570 ; data[4] ; a6~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.380 ;
|
|
; 0.572 ; data[7] ; a9~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.378 ;
|
|
; 0.572 ; data[7] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.378 ;
|
|
; 0.591 ; data[0] ; data[0] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 1.000 ; -0.037 ; 0.359 ;
|
|
+--------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Hold: 'clk' ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
; -0.129 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; 0.000 ; 1.181 ; 1.271 ;
|
|
; 0.262 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.383 ;
|
|
; 0.298 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.419 ;
|
|
; 0.298 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.419 ;
|
|
; 0.298 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.419 ;
|
|
; 0.298 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.419 ;
|
|
; 0.299 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.037 ; 0.420 ;
|
|
; 0.308 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[0] ; clk ; clk ; 0.000 ; 0.037 ; 0.429 ;
|
|
; 0.447 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.568 ;
|
|
; 0.447 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.568 ;
|
|
; 0.448 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.037 ; 0.569 ;
|
|
; 0.450 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.571 ;
|
|
; 0.451 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.572 ;
|
|
; 0.456 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.577 ;
|
|
; 0.456 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.577 ;
|
|
; 0.456 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.577 ;
|
|
; 0.457 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.578 ;
|
|
; 0.459 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.580 ;
|
|
; 0.460 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[2] ; clk ; clk ; 0.000 ; 0.037 ; 0.581 ;
|
|
; 0.463 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.584 ;
|
|
; 0.493 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; clk ; -0.500 ; 1.181 ; 1.393 ;
|
|
; 0.510 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.631 ;
|
|
; 0.510 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.631 ;
|
|
; 0.511 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.632 ;
|
|
; 0.513 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.634 ;
|
|
; 0.513 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.634 ;
|
|
; 0.522 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.643 ;
|
|
; 0.523 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.644 ;
|
|
; 0.526 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.647 ;
|
|
; 0.526 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.647 ;
|
|
; 0.529 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.650 ;
|
|
; 0.576 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.697 ;
|
|
; 0.576 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.697 ;
|
|
; 0.579 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.700 ;
|
|
; 0.580 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.701 ;
|
|
; 0.589 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.710 ;
|
|
; 0.591 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.712 ;
|
|
; 0.592 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.713 ;
|
|
; 0.592 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.713 ;
|
|
; 0.592 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.713 ;
|
|
; 0.593 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.714 ;
|
|
; 0.597 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.718 ;
|
|
; 0.601 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.722 ;
|
|
; 0.612 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.733 ;
|
|
; 0.614 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.735 ;
|
|
; 0.630 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.751 ;
|
|
; 0.635 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.756 ;
|
|
; 0.636 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.757 ;
|
|
; 0.642 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.763 ;
|
|
; 0.643 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.764 ;
|
|
; 0.646 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.767 ;
|
|
; 0.655 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.776 ;
|
|
; 0.655 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[7] ; clk ; clk ; 0.000 ; 0.037 ; 0.776 ;
|
|
; 0.658 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[8] ; clk ; clk ; 0.000 ; 0.037 ; 0.779 ;
|
|
; 0.662 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.783 ;
|
|
; 0.675 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.796 ;
|
|
; 0.696 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 0.817 ;
|
|
; 0.709 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.830 ;
|
|
; 0.721 ; div_clk:div_clk_inst|count[0] ; div_clk:div_clk_inst|count[9] ; clk ; clk ; 0.000 ; 0.037 ; 0.842 ;
|
|
; 0.725 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.846 ;
|
|
; 0.738 ; div_clk:div_clk_inst|count[1] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 0.859 ;
|
|
; 0.738 ; div_clk:div_clk_inst|count[4] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 0.859 ;
|
|
; 0.745 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.866 ;
|
|
; 0.747 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.868 ;
|
|
; 0.786 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.907 ;
|
|
; 0.788 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.909 ;
|
|
; 0.792 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.913 ;
|
|
; 0.792 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.913 ;
|
|
; 0.810 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.931 ;
|
|
; 0.812 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.933 ;
|
|
; 0.816 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.937 ;
|
|
; 0.828 ; div_clk:div_clk_inst|count[2] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 0.949 ;
|
|
; 0.850 ; div_clk:div_clk_inst|count[5] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 0.971 ;
|
|
; 0.880 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 1.001 ;
|
|
; 0.882 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 1.003 ;
|
|
; 0.882 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[4] ; clk ; clk ; 0.000 ; 0.037 ; 1.003 ;
|
|
; 0.884 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[1] ; clk ; clk ; 0.000 ; 0.037 ; 1.005 ;
|
|
; 0.886 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 1.007 ;
|
|
; 0.888 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|count[5] ; clk ; clk ; 0.000 ; 0.037 ; 1.009 ;
|
|
; 0.891 ; div_clk:div_clk_inst|count[6] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 1.012 ;
|
|
; 0.898 ; div_clk:div_clk_inst|count[3] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 1.019 ;
|
|
; 0.917 ; div_clk:div_clk_inst|count[9] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 1.038 ;
|
|
; 0.985 ; div_clk:div_clk_inst|count[7] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 1.106 ;
|
|
; 0.990 ; div_clk:div_clk_inst|count[8] ; div_clk:div_clk_inst|clk_div ; clk ; clk ; 0.000 ; 0.037 ; 1.111 ;
|
|
+--------+-------------------------------+-------------------------------+------------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Hold: 'div_clk:div_clk_inst|clk_div' ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
; 0.193 ; data[0] ; data[0] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.314 ;
|
|
; 0.196 ; data[7] ; a9~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.317 ;
|
|
; 0.197 ; data[7] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.318 ;
|
|
; 0.198 ; data[4] ; a6~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.319 ;
|
|
; 0.271 ; data[6] ; a8~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.036 ; 0.391 ;
|
|
; 0.281 ; data[5] ; a7~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.036 ; 0.401 ;
|
|
; 0.298 ; data[4] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.419 ;
|
|
; 0.304 ; data[6] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.425 ;
|
|
; 0.305 ; data[2] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.426 ;
|
|
; 0.306 ; data[3] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.427 ;
|
|
; 0.307 ; data[5] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.428 ;
|
|
; 0.311 ; data[1] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.432 ;
|
|
; 0.312 ; data[0] ; data[1] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.433 ;
|
|
; 0.331 ; data[3] ; a5~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.452 ;
|
|
; 0.331 ; data[1] ; a3~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.452 ;
|
|
; 0.332 ; data[0] ; a2~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.453 ;
|
|
; 0.345 ; data[2] ; a4~reg0 ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.466 ;
|
|
; 0.447 ; data[4] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.568 ;
|
|
; 0.453 ; data[6] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.574 ;
|
|
; 0.454 ; data[2] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.575 ;
|
|
; 0.463 ; data[1] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.584 ;
|
|
; 0.464 ; data[3] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.585 ;
|
|
; 0.465 ; data[5] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.586 ;
|
|
; 0.465 ; data[0] ; data[2] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.586 ;
|
|
; 0.466 ; data[1] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.587 ;
|
|
; 0.467 ; data[3] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.588 ;
|
|
; 0.468 ; data[5] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.589 ;
|
|
; 0.468 ; data[0] ; data[3] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.589 ;
|
|
; 0.510 ; data[4] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.631 ;
|
|
; 0.513 ; data[4] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.634 ;
|
|
; 0.517 ; data[2] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.638 ;
|
|
; 0.520 ; data[2] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.641 ;
|
|
; 0.529 ; data[1] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.650 ;
|
|
; 0.530 ; data[3] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.651 ;
|
|
; 0.531 ; data[0] ; data[4] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.652 ;
|
|
; 0.532 ; data[1] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.653 ;
|
|
; 0.533 ; data[3] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.654 ;
|
|
; 0.534 ; data[0] ; data[5] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.655 ;
|
|
; 0.583 ; data[2] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.704 ;
|
|
; 0.586 ; data[2] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.707 ;
|
|
; 0.595 ; data[1] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.716 ;
|
|
; 0.597 ; data[0] ; data[6] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.718 ;
|
|
; 0.598 ; data[1] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.719 ;
|
|
; 0.600 ; data[0] ; data[7] ; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 0.000 ; 0.037 ; 0.721 ;
|
|
+-------+-----------+---------+------------------------------+------------------------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk' ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; clk ; Rise ; clk ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; -0.065 ; 0.119 ; 0.184 ; Low Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|clk_div|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[0]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[1]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[2]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[3]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[4]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[5]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[6]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[7]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[8]|clk ;
|
|
; 0.115 ; 0.115 ; 0.000 ; Low Pulse Width ; clk ; Rise ; div_clk_inst|count[9]|clk ;
|
|
; 0.120 ; 0.120 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~input|o ;
|
|
; 0.139 ; 0.139 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~inputclkctrl|inclk[0] ;
|
|
; 0.139 ; 0.139 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~inputclkctrl|outclk ;
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~input|i ;
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~input|i ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[0] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[1] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[2] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[3] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[4] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[5] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[6] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[7] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[8] ;
|
|
; 0.663 ; 0.879 ; 0.216 ; High Pulse Width ; clk ; Rise ; div_clk:div_clk_inst|count[9] ;
|
|
; 0.861 ; 0.861 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~inputclkctrl|inclk[0] ;
|
|
; 0.861 ; 0.861 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~inputclkctrl|outclk ;
|
|
; 0.880 ; 0.880 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~input|o ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|clk_div|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[0]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[1]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[2]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[3]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[4]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[5]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[6]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[7]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[8]|clk ;
|
|
; 0.885 ; 0.885 ; 0.000 ; High Pulse Width ; clk ; Rise ; div_clk_inst|count[9]|clk ;
|
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Fast 1200mV 0C Model Minimum Pulse Width: 'div_clk:div_clk_inst|clk_div' ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; 0.266 ; 0.450 ; 0.184 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0 ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6] ;
|
|
; 0.331 ; 0.547 ; 0.216 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7] ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6]|clk ;
|
|
; 0.446 ; 0.446 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7]|clk ;
|
|
; 0.468 ; 0.468 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|inclk[0] ;
|
|
; 0.468 ; 0.468 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|outclk ;
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div|q ;
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div|q ;
|
|
; 0.532 ; 0.532 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|inclk[0] ;
|
|
; 0.532 ; 0.532 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; div_clk_inst|clk_div~clkctrl|outclk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a2~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a3~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a4~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a5~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a6~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a7~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a8~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; a9~reg0|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[0]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[1]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[2]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[3]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[4]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[5]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[6]|clk ;
|
|
; 0.553 ; 0.553 ; 0.000 ; High Pulse Width ; div_clk:div_clk_inst|clk_div ; Rise ; data[7]|clk ;
|
|
+--------+--------------+----------------+------------------+------------------------------+------------+---------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 3.176 ; 3.225 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 3.283 ; 3.346 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 3.171 ; 3.223 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 3.155 ; 3.203 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 3.064 ; 3.106 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 3.037 ; 3.077 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 3.295 ; 3.356 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 3.322 ; 3.390 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Minimum Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 3.062 ; 3.109 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 3.164 ; 3.224 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 3.057 ; 3.107 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 3.041 ; 3.087 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 2.954 ; 2.994 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 2.927 ; 2.966 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 3.174 ; 3.233 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 3.201 ; 3.267 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
---------------------------------------------
|
|
; Fast 1200mV 0C Model Metastability Report ;
|
|
---------------------------------------------
|
|
No synchronizer chains to report.
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------+
|
|
; Multicorner Timing Analysis Summary ;
|
|
+-------------------------------+---------+--------+----------+---------+---------------------+
|
|
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
|
+-------------------------------+---------+--------+----------+---------+---------------------+
|
|
; Worst-case Slack ; -1.975 ; -0.129 ; N/A ; N/A ; -3.000 ;
|
|
; clk ; -1.975 ; -0.129 ; N/A ; N/A ; -3.000 ;
|
|
; div_clk:div_clk_inst|clk_div ; -1.342 ; 0.193 ; N/A ; N/A ; -1.487 ;
|
|
; Design-wide TNS ; -23.952 ; -0.129 ; 0.0 ; 0.0 ; -43.149 ;
|
|
; clk ; -15.066 ; -0.129 ; N/A ; N/A ; -19.357 ;
|
|
; div_clk:div_clk_inst|clk_div ; -8.886 ; 0.000 ; N/A ; N/A ; -23.792 ;
|
|
+-------------------------------+---------+--------+----------+---------+---------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 6.813 ; 6.674 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 7.120 ; 6.921 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 6.842 ; 6.691 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 6.784 ; 6.649 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 6.552 ; 6.455 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 6.501 ; 6.407 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 7.149 ; 6.967 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 7.209 ; 7.015 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------+
|
|
; Minimum Clock to Output Times ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
; a2 ; div_clk:div_clk_inst|clk_div ; 3.062 ; 3.109 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a3 ; div_clk:div_clk_inst|clk_div ; 3.164 ; 3.224 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a4 ; div_clk:div_clk_inst|clk_div ; 3.057 ; 3.107 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a5 ; div_clk:div_clk_inst|clk_div ; 3.041 ; 3.087 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a6 ; div_clk:div_clk_inst|clk_div ; 2.954 ; 2.994 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a7 ; div_clk:div_clk_inst|clk_div ; 2.927 ; 2.966 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a8 ; div_clk:div_clk_inst|clk_div ; 3.174 ; 3.233 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
; a9 ; div_clk:div_clk_inst|clk_div ; 3.201 ; 3.267 ; Rise ; div_clk:div_clk_inst|clk_div ;
|
|
+-----------+------------------------------+-------+-------+------------+------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Board Trace Model Assignments ;
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
|
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
|
; a2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a4 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a5 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a6 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a7 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a8 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; a9 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
; Input Transition Times ;
|
|
+-------------------------+--------------+-----------------+-----------------+
|
|
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
|
+-------------------------+--------------+-----------------+-----------------+
|
|
; rst_n ; 2.5 V ; 2000 ps ; 2000 ps ;
|
|
; clk ; 2.5 V ; 2000 ps ; 2000 ps ;
|
|
; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
|
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
|
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
|
+-------------------------+--------------+-----------------+-----------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; a2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a4 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a5 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a6 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a7 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a8 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; a9 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ;
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; a2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a4 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a5 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a6 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a7 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a8 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; a9 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ;
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; a2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a4 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a5 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a6 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a7 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a8 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; a9 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------+
|
|
; Setup Transfers ;
|
|
+------------------------------+------------------------------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------------------------+------------------------------+----------+----------+----------+----------+
|
|
; clk ; clk ; 95 ; 0 ; 0 ; 0 ;
|
|
; div_clk:div_clk_inst|clk_div ; clk ; 1 ; 1 ; 0 ; 0 ;
|
|
; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 44 ; 0 ; 0 ; 0 ;
|
|
+------------------------------+------------------------------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------+
|
|
; Hold Transfers ;
|
|
+------------------------------+------------------------------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------------------------+------------------------------+----------+----------+----------+----------+
|
|
; clk ; clk ; 95 ; 0 ; 0 ; 0 ;
|
|
; div_clk:div_clk_inst|clk_div ; clk ; 1 ; 1 ; 0 ; 0 ;
|
|
; div_clk:div_clk_inst|clk_div ; div_clk:div_clk_inst|clk_div ; 44 ; 0 ; 0 ; 0 ;
|
|
+------------------------------+------------------------------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
---------------
|
|
; Report TCCS ;
|
|
---------------
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
|
|
|
|
|
---------------
|
|
; Report RSKM ;
|
|
---------------
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
|
|
|
|
|
+------------------------------------------------+
|
|
; Unconstrained Paths ;
|
|
+---------------------------------+-------+------+
|
|
; Property ; Setup ; Hold ;
|
|
+---------------------------------+-------+------+
|
|
; Illegal Clocks ; 0 ; 0 ;
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
|
; Unconstrained Input Ports ; 1 ; 1 ;
|
|
; Unconstrained Input Port Paths ; 27 ; 27 ;
|
|
; Unconstrained Output Ports ; 8 ; 8 ;
|
|
; Unconstrained Output Port Paths ; 8 ; 8 ;
|
|
+---------------------------------+-------+------+
|
|
|
|
|
|
+------------------------------------+
|
|
; TimeQuest Timing Analyzer Messages ;
|
|
+------------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
|
|
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
|
Info: Processing started: Sat Aug 03 00:24:20 2024
|
|
Info: Command: quartus_sta test -c test
|
|
Info: qsta_default_script.tcl version: #1
|
|
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
|
|
Info (21077): Core supply voltage is 1.2V
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 85 degrees C
|
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
|
Info (332105): Deriving Clocks
|
|
Info (332105): create_clock -period 1.000 -name div_clk:div_clk_inst|clk_div div_clk:div_clk_inst|clk_div
|
|
Info (332105): create_clock -period 1.000 -name clk clk
|
|
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
|
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
|
Info: Analyzing Slow 1200mV 85C Model
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
|
Info (332146): Worst-case setup slack is -1.975
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -1.975 -15.066 clk
|
|
Info (332119): -1.342 -8.886 div_clk:div_clk_inst|clk_div
|
|
Info (332146): Worst-case hold slack is 0.029
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.029 0.000 clk
|
|
Info (332119): 0.464 0.000 div_clk:div_clk_inst|clk_div
|
|
Info (332140): No Recovery paths to report
|
|
Info (332140): No Removal paths to report
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -3.000 -19.357 clk
|
|
Info (332119): -1.487 -23.792 div_clk:div_clk_inst|clk_div
|
|
Info: Analyzing Slow 1200mV 0C Model
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
|
Info (332146): Worst-case setup slack is -1.769
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -1.769 -12.679 clk
|
|
Info (332119): -1.095 -6.926 div_clk:div_clk_inst|clk_div
|
|
Info (332146): Worst-case hold slack is 0.114
|
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Info (332119): Slack End Point TNS Clock
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Info (332119): ========= =================== =====================
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Info (332119): 0.114 0.000 clk
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Info (332119): 0.416 0.000 div_clk:div_clk_inst|clk_div
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Info (332140): No Recovery paths to report
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Info (332140): No Removal paths to report
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Info (332146): Worst-case minimum pulse width slack is -3.000
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Info (332119): Slack End Point TNS Clock
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Info (332119): ========= =================== =====================
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Info (332119): -3.000 -19.357 clk
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Info (332119): -1.487 -23.792 div_clk:div_clk_inst|clk_div
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Info: Analyzing Fast 1200mV 0C Model
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Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
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Critical Warning (332148): Timing requirements not met
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Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
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Info (332146): Worst-case setup slack is -0.231
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Info (332119): Slack End Point TNS Clock
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Info (332119): ========= =================== =====================
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Info (332119): -0.231 -0.813 clk
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Info (332119): -0.022 -0.022 div_clk:div_clk_inst|clk_div
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Info (332146): Worst-case hold slack is -0.129
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Info (332119): Slack End Point TNS Clock
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Info (332119): ========= =================== =====================
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Info (332119): -0.129 -0.129 clk
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Info (332119): 0.193 0.000 div_clk:div_clk_inst|clk_div
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Info (332140): No Recovery paths to report
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Info (332140): No Removal paths to report
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Info (332146): Worst-case minimum pulse width slack is -3.000
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Info (332119): Slack End Point TNS Clock
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Info (332119): ========= =================== =====================
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Info (332119): -3.000 -14.715 clk
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Info (332119): -1.000 -16.000 div_clk:div_clk_inst|clk_div
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Info (332102): Design is not fully constrained for setup requirements
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Info (332102): Design is not fully constrained for hold requirements
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Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
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Info: Peak virtual memory: 4762 megabytes
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Info: Processing ended: Sat Aug 03 00:24:21 2024
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:02
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