FPGA_module/test/par/output_files/test.jdi

<sld_project_info>
  <project>
    <hash md5_digest_80b="ab5557854ccc8d571df5"/>
  </project>
  <file_info>
    <file device="EP4CE10F17C8" path="test.sof" usercode="0xFFFFFFFF"/>
  </file_info>
</sld_project_info>