117 lines
6.7 KiB
Plaintext
117 lines
6.7 KiB
Plaintext
Assembler report for test
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Sat Aug 03 00:24:19 2024
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Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Assembler Summary
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3. Assembler Settings
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4. Assembler Generated Files
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5. Assembler Device Options: E:/FPGA/FPGA_lib/test/par/output_files/test.sof
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6. Assembler Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Sat Aug 03 00:24:19 2024 ;
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; Revision Name ; test ;
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; Top-level Entity Name ; test_top ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE10F17C8 ;
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+-----------------------+---------------------------------------+
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+--------------------------------------------------------------------------------------------------------+
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; Assembler Settings ;
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+-----------------------------------------------------------------------------+----------+---------------+
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; Option ; Setting ; Default Value ;
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+-----------------------------------------------------------------------------+----------+---------------+
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Generate compressed bitstreams ; On ; On ;
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; Compression mode ; Off ; Off ;
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; Clock source for configuration device ; Internal ; Internal ;
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; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
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; Divide clock frequency by ; 1 ; 1 ;
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; Auto user code ; On ; On ;
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; Use configuration device ; Off ; Off ;
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; Configuration device ; Auto ; Auto ;
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; Configuration device auto user code ; Off ; Off ;
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; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
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; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
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; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
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; Hexadecimal Output File start address ; 0 ; 0 ;
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; Hexadecimal Output File count direction ; Up ; Up ;
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; Release clears before tri-states ; Off ; Off ;
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; Auto-restart configuration after error ; On ; On ;
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; Enable OCT_DONE ; Off ; Off ;
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; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
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; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
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; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
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; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
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+-----------------------------------------------------------------------------+----------+---------------+
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+-------------------------------------------------+
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; Assembler Generated Files ;
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+-------------------------------------------------+
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; File Name ;
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+-------------------------------------------------+
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; E:/FPGA/FPGA_lib/test/par/output_files/test.sof ;
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+-------------------------------------------------+
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+---------------------------------------------------------------------------+
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; Assembler Device Options: E:/FPGA/FPGA_lib/test/par/output_files/test.sof ;
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+----------------+----------------------------------------------------------+
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; Option ; Setting ;
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+----------------+----------------------------------------------------------+
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; Device ; EP4CE10F17C8 ;
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; JTAG usercode ; 0x0008B5F5 ;
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; Checksum ; 0x0008B5F5 ;
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+----------------+----------------------------------------------------------+
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+--------------------+
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; Assembler Messages ;
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus II 64-Bit Assembler
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
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Info: Processing started: Sat Aug 03 00:24:18 2024
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off test -c test
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 4590 megabytes
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Info: Processing ended: Sat Aug 03 00:24:19 2024
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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