87 lines
2.3 KiB
Verilog
87 lines
2.3 KiB
Verilog
module uart_tx (
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input wire clk,
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input wire rstn,
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input wire en,
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input wire tx_req_start,
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input wire[7:0] tx_data,
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output reg tx_ply_ok,
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output reg tx_busy,
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output reg tx_pin
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);
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parameter DIV = 50;
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parameter COUNT_WITH = 6;
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reg [COUNT_WITH-1:0] count;
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reg [7:0] data_reg;
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reg [3:0] tx_count;
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reg[2:0] state;
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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tx_pin <= 1'b1;
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count <= 0;
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tx_count <= 0;
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state <= 0;
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data_reg <= 0;
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tx_ply_ok <= 0;
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end else begin
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if (en == 0) begin
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tx_pin <= 1'b1;
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count <= 0;
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tx_count <= 0;
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state <= 0;
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data_reg <= 0;
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tx_ply_ok <= 0;
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end else begin
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case (state)
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0: begin
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if (tx_req_start) begin
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data_reg <= tx_data;
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state <= 1;
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end
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tx_ply_ok <= 0;
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tx_pin <= 1'b1;
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tx_count <= 0;
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end
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1: begin
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tx_ply_ok <= 1'b1;
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tx_pin <= 1'b0;
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tx_count <= 1'b0;
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if(count == DIV-1) begin
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state <= 2;
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count <= 0;
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end else begin
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count <= count + 1'd1;
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end
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end
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2: begin
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tx_ply_ok <= 1'b0;
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tx_pin <= data_reg[tx_count];
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if(count == DIV-1) begin
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count <= 0;
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tx_count <= tx_count + 1'd1;
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end else begin
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count <= count + 1'd1;
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end
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if(tx_count == 8) begin
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state <= 3;
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tx_pin <= 1'b1;
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end
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end
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3: begin
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if(count == DIV-1) begin
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count <= 0;
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state <= 0;
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end else begin
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count <= count + 1'd1;
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end
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end
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endcase
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end
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end
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end
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endmodule |