44 lines
881 B
Coq
44 lines
881 B
Coq
module uart_top(
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input wire clk,
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input wire rst_n,
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output wire tx
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);
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reg uart_tx_start;
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reg [7:0] uart_tx_data;
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wire uart_busy;
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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uart_tx_start <= 1'b0;
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uart_tx_data <= 8'd0;
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end
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else begin
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if(uart_busy == 1'b0) begin
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if(uart_tx_start == 1'b0) begin
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uart_tx_start <= 1'b1;
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uart_tx_data <= 8'd0;
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uart_tx_data <= uart_tx_data + 8'd1;
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end
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else begin
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uart_tx_start <= uart_tx_start;
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end
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end
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else begin
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uart_tx_start <= 1'b0;
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end
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end
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end
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uart_tx uart_tx_tb0(
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.clk(clk),
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.rst_n(rst_n),
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.tx_en(1'b1),
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.tx_start(uart_tx_start),
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.tx_data(uart_tx_data),
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.uart_busy(uart_busy),
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.tx(tx)
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);
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endmodule |