63 lines
1.2 KiB
Verilog
63 lines
1.2 KiB
Verilog
module uart_top(
|
|
input wire clk,
|
|
input wire rstn,
|
|
input wire rx_pin,
|
|
output wire tx_pin
|
|
);
|
|
|
|
wire tx_busy;
|
|
wire tx_ply_ok;
|
|
reg tx_req_start;
|
|
reg[7:0] tx_data;
|
|
uart_tx uart_tx_c0(
|
|
.clk(clk),
|
|
.rstn(rstn),
|
|
.en(1'b1),
|
|
.tx_req_start(tx_req_start),
|
|
.tx_data(tx_data),
|
|
.tx_pin(tx_pin),
|
|
.tx_busy(tx_busy),
|
|
.tx_ply_ok(tx_ply_ok)
|
|
);
|
|
|
|
wire rx_rdy;
|
|
wire[7:0] rx_data;
|
|
uart_rx uart_rx_c0(
|
|
.clk(clk),
|
|
.rst_n(rstn),
|
|
.rx_en(1'b1),
|
|
.rx_pin(rx_pin),
|
|
.rx_rdy(rx_rdy),
|
|
.rx_data(rx_data)
|
|
);
|
|
reg[2:0] state;
|
|
|
|
always @(posedge clk or negedge rstn) begin
|
|
if(~rstn) begin
|
|
state <= 0;
|
|
tx_req_start <= 0;
|
|
tx_data <= 0;
|
|
end else begin
|
|
case(state)
|
|
0: begin
|
|
if(rx_rdy) begin
|
|
tx_req_start <= 1;
|
|
tx_data <= rx_data;
|
|
state <= 1;
|
|
end
|
|
end
|
|
1: begin
|
|
if(tx_ply_ok) begin
|
|
tx_req_start <= 0;
|
|
state <= 2;
|
|
end
|
|
end
|
|
2: begin
|
|
if(tx_ply_ok == 0)begin
|
|
state <= 0;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
endmodule |