20 lines
8.0 KiB
Plaintext
20 lines
8.0 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1723128452793 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1723128452793 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 08 22:47:32 2024 " "Processing started: Thu Aug 08 22:47:32 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1723128452793 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1723128452793 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off excute -c excute " "Command: quartus_map --read_settings_files=on --write_settings_files=off excute -c excute" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1723128452794 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1723128452988 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/work/fpga/fpga_module/uart/uart_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /work/fpga/fpga_module/uart/uart_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" { } { { "../uart_rx.v" "" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_rx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1723128453080 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1723128453080 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/work/fpga/fpga_module/uart/div_clk.v 1 1 " "Found 1 design units, including 1 entities, in source file /work/fpga/fpga_module/uart/div_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_clk " "Found entity 1: div_clk" { } { { "../div_clk.v" "" { Text "D:/WORK/FPGA/FPGA_module/uart/div_clk.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1723128453081 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1723128453081 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/work/fpga/fpga_module/uart/uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /work/fpga/fpga_module/uart/uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "../uart_tx.v" "" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_tx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1723128453083 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1723128453083 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/work/fpga/fpga_module/uart/uart_top.v 1 1 " "Found 1 design units, including 1 entities, in source file /work/fpga/fpga_module/uart/uart_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_top " "Found entity 1: uart_top" { } { { "../uart_top.v" "" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1723128453084 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1723128453084 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "uart_top " "Elaborating entity \"uart_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1723128453117 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:uart_tx_c0 " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:uart_tx_c0\"" { } { { "../uart_top.v" "uart_tx_c0" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_top.v" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1723128453128 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_busy uart_tx.v(8) " "Output port \"tx_busy\" at uart_tx.v(8) has no driver" { } { { "../uart_tx.v" "" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_tx.v" 8 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1723128453129 "|uart_top|uart_tx:uart_tx_c0"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart_rx:uart_rx_c0 " "Elaborating entity \"uart_rx\" for hierarchy \"uart_rx:uart_rx_c0\"" { } { { "../uart_top.v" "uart_rx_c0" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_top.v" 32 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1723128453131 ""}
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{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../uart_tx.v" "" { Text "D:/WORK/FPGA/FPGA_module/uart/uart_tx.v" 10 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1723128453532 ""}
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{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1723128453532 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1723128453666 ""}
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1723128453790 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1723128453923 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1723128453923 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "118 " "Implemented 118 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1723128453997 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1723128453997 ""} { "Info" "ICUT_CUT_TM_LCELLS" "114 " "Implemented 114 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1723128453997 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1723128453997 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4658 " "Peak virtual memory: 4658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1723128454005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 08 22:47:34 2024 " "Processing ended: Thu Aug 08 22:47:34 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1723128454005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1723128454005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1723128454005 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1723128454005 ""}
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