21 lines
442 B
Verilog
21 lines
442 B
Verilog
module div_clk(input clk, rstn, output reg clk_div);
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parameter DIV = 10;
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parameter COUNT_WITH = 10;
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reg [COUNT_WITH-1:0] count;
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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count <= 0;
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clk_div <= 0;
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end else begin
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if (count == (DIV-1)) begin
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count <= 0;
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clk_div <= ~clk_div;
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end else begin
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count <= count + 1'd1;
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end
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end
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end
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endmodule |