40 lines
722 B
Coq
40 lines
722 B
Coq
module test_top (
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input wire clk,
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input wire rst_n,
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output wire a2,
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output wire a3,
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output wire a4,
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output wire a5,
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output wire a6,
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output wire a7,
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output wire a8,
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output wire a9
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);
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wire clk_low;
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div_clk #(
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.COUNT_WITH(10),
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.DIV(50)
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) div_clk_inst (
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.clk(clk),
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.rst_n(rst_n),
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.clk_div(clk_low),
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);
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assign a2 = data[0];
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assign a3 = data[1];
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assign a4 = data[2];
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assign a5 = data[3];
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assign a6 = data[4];
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assign a7 = data[5];
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assign a8 = data[6];
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assign a9 = data[7];
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reg [7:0] data;
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always @(posedge clk_low or negedge rst_n) begin
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if (!rst_n) begin
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data <= 8'd0;
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end
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else begin
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data <= data + 1'b1;
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end
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end
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endmodule //test_top |