FPGA_module/clk/outclk.v

50 lines
1.5 KiB
Coq

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "E:\iverilog\lib\ivl\system.vpi";
:vpi_module "E:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "E:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "E:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "E:\iverilog\lib\ivl\va_math.vpi";
S_0000022e5e572830 .scope module, "clk_tb" "clk_tb" 2 4;
.timescale -9 -12;
v0000022e5e5729c0_0 .var "clk", 0 0;
v0000022e5e572a60_0 .var "rst", 0 0;
.scope S_0000022e5e572830;
T_0 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000022e5e5729c0_0, 0, 1;
%end;
.thread T_0;
.scope S_0000022e5e572830;
T_1 ;
%delay 5000, 0;
%load/vec4 v0000022e5e5729c0_0;
%inv;
%store/vec4 v0000022e5e5729c0_0, 0, 1;
%jmp T_1;
.thread T_1;
.scope S_0000022e5e572830;
T_2 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000022e5e572a60_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000022e5e572a60_0, 0, 1;
%end;
.thread T_2;
.scope S_0000022e5e572830;
T_3 ;
%vpi_call 2 22 "$dumpfile", "clk_tb.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000022e5e572830 {0 0 0};
%delay 1000000, 0;
%vpi_call 2 24 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"clk_tb.v";