FPGA_module/clk/clk_test.v

module clk_test (
    input  wire clk,
    input  wire rst_n
);

reg clk_out;


always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        clk_out <= 0;
    end else begin
        if (clk_out == 1'b0) begin
            clk_out <= 1'b1;
        end else begin
            clk_out <= 1'b0;
        end
    end
end


endmodule //clk_test