533 lines
2.8 KiB
Plaintext
533 lines
2.8 KiB
Plaintext
$date
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Tue Jul 30 20:27:09 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module clk_tb $end
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$var wire 1 ! rst $end
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$var reg 1 " clk $end
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$var reg 1 # rst_n $end
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$scope module tb_clk $end
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$var wire 1 " clk $end
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$var wire 1 ! rst_n $end
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$var reg 1 $ clk_out $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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x$
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1#
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0"
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z!
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$end
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1#
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0$
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1$
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0$
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1$
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0$
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1"
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1$
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0$
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0"
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1$
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0"
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0$
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1$
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0"
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0$
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1$
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0$
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0$
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1"
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0$
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1$
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1$
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0$
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1"
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1$
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1"
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0$
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1"
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1$
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1"
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0$
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1"
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1$
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1"
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#940000
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0$
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1"
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#950000
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0"
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#955000
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1$
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1"
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#960000
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0"
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0$
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1"
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#970000
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0"
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1$
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1"
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#980000
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0"
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#985000
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0$
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1"
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#990000
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0"
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#995000
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1$
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1"
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#1000000
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0"
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