33 lines
337 B
Verilog
33 lines
337 B
Verilog
`timescale 1ns/1ps
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module clk_tb;
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reg clk, rst_n;
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initial begin
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clk = 0;
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end
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always #5 clk = ~clk;
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initial begin
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rst_n = 1;
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#10 rst_n = 0;
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#10 rst_n = 1;
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end
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clk_test tb_clk(
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.clk(clk),
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.rst_n(rst)
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);
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initial begin
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$dumpfile("clk_tb.vcd");
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$dumpvars(0, clk_tb);
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#1000 $finish;
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end
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endmodule |