module uart_top(
    input wire clk,
    input wire rst_n,
    output wire clk_uart_tx,
    output wire tx_pin,
    output wire tx_busy,
    input wire rx_pin,
    output wire[7:0] rx_data,
    output wire rx_rdy
);


// assign clk_uart_tx = clk;

div_clk #(
    .COUNT_WITH (6),
    .DIV (6'd50)
)
uart_div_c0(
    .clk(clk),
    .rst_n(rst_n),
    .clk_div(clk_uart_tx)
);

reg send_flag;
reg[7:0] send_data;
reg send_state;
parameter SEND_IDLE = 1'd0;
parameter SEND_START = 1'd1;
reg[1:0] rx_rdy_state;
reg[1:0] tx_busy_state;
always (posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        send_state <= SEND_IDLE;
    end
    else begin
        rx_rdy_state[0] <= rx_rdy;
        rx_rdy_state[1] <= rx_rdy_state[0];
        rx_rdy <= rx_rdy_state[1];
        tx_busy_state[0] <= tx_busy;
        case(send_state)
            SEND_IDLE: begin
                if(rx_rdy_state[1]==1'b0 && rx_rdy_state[0]==1'b1) begin
                    send_state <= SEND_START;
                end
            end
            SEND_START: begin

            end
            default:send_state <= send_state;
        endcase
    end
end


uart_tx uart_tx_c0(
    .clk(clk_uart_tx),
    .rst_n(rst_n),
    .tx_en(1'b1),
    .tx_start(send_flag),
    .tx_data(send_data),
    .tx_busy(tx_busy),
    .tx_out(tx_pin)
);
uart_rx uart_rx_c0(
    .clk(clk_uart_tx),
    .rst_n(rst_n),
    .rx_en(1'b1),
    .rx_data(rx_data),
    .rx_rdy(rx_rdy),
    .rx(rx_pin)
);
// reg [1:0] uart_send_state;
// reg [1:0] uart_send_next_state;
// parameter UART_OFF = 2'd0;
// parameter UART_SEND = 2'd1;
// parameter UART_WAIT = 2'd2;

// always @ (posedge clk or negedge rst_n) begin
//     if(~rst_n) begin
//         uart_send_state <= UART_OFF;
//     end else begin
//         uart_send_state <= uart_send_next_state;
//     end
// end
// always@(*) begin
//     case(uart_send_state)
//         UART_OFF: begin
//             uart_send_next_state <= UART_SEND;
//         end
//         UART_SEND: begin
//             if(tx_busy == 1'd1) begin
//                 uart_send_next_state <= UART_WAIT;
//             end
//             else begin
//                 uart_send_next_state <= UART_SEND;
//             end
//         end
//         UART_WAIT: begin
//             if(tx_busy == 1'd0) begin
//                 uart_send_next_state <= UART_SEND;
//             end
//             else begin
//                 uart_send_next_state <= UART_WAIT;
//             end
//         end
//         default : uart_send_next_state <= uart_send_next_state;
//     endcase
// end
// always @( *) begin
//     case(uart_send_state)
//         UART_OFF: tx_en <= 1'b0;
//         UART_SEND: tx_en <= 1'b1;
//         UART_WAIT: tx_en <= 1'b1;
//         default : tx_en <= 1'b1;
//     endcase
// end
// always @(posedge clk or negedge rst_n) begin
//     if(~rst_n) begin
//         tx_start <= 1'b0;
//         tx_data <= 8'b0;
//     end
//     else begin
//         case(uart_send_state)
//             UART_OFF: begin 
//                 tx_start <= 1'b0;
//                 tx_data <= 8'b0;
//             end
//             UART_SEND:begin  
//                 if(tx_start == 1'b0) begin
//                     tx_start <= 1'b1;
//                     tx_data <= tx_data + 1'b1;
//                 end
//                 else begin
//                     tx_start <= 1'b1;
//                     tx_data <= tx_data;
//                 end
//             end
//             UART_WAIT:  begin 
//                 tx_start <= 1'b0;
//                 tx_data <= tx_data;
//             end
//             default:   begin 
//                 tx_start <= 1'b0;
//                 tx_data <= tx_data;
//             end
//         endcase
//     end
// end
endmodule