module uart_rx(
    input  wire        clk,
    input  wire        rst_n,
    input  wire        rx_en,
    input  wire        rx,
    output wire        rx_rdy,
    output wire [7:0]  rx_data
);

reg [7:0] rx_reg;
reg [4:0] rx_cnt;

reg [1:0] state;
reg [1:0] state_next;
parameter STOP = 2'd0, IDLE = 2'd1, DATA = 2'd2;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        state <= STOP;
    end
    else begin
        state <= state_next;
    end
end

always @( *) begin
    if(rx_en == 1'd0) begin
        state_next = STOP;
    end
    else begin
        case(state)
            default state_next <= state_next;
            STOP: state_next <= IDLE;
            IDLE: begin 
                if(rx == 1'd0) state_next <= DATA;
                else  state_next <= IDLE;
            end
            DATA: begin 
                if(rx_cnt == 5'd10) state_next <= IDLE;
                else state_next <= DATA;
            end
        endcase
    end
end
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        rx_rdy <= 1'd0;
        rx_data <= 8'd0;
        rx_cnt <= 5'd0;
    end
    else begin
        case(state)
            default rx_rdy <= 1'd0;
            STOP: begin
                rx_rdy <= 1'd0;
                rx_data <= 8'd0;
                rx_cnt <= 5'd0;
            end
            IDLE : begin
                rx_rdy <= rx_rdy;
                rx_data <= 8'd0;
                rx_cnt <= 5'd0;
            end
            DATA: begin
                if(rx_cnt == 5'd0) begin
                    rx_cnt <= rx_cnt + 1'd1;
                end
                else if (rx_cnt < 5'd9) begin
                    rx_reg[rx_cnt-1'd1] <= rx;
                    rx_cnt <= rx_cnt + 1'd1;
                end
                else if (rx_cnt == 5'd9) begin
                    rx_cnt <= rx_cnt + 1'd1;
                    rx_rdy <= 1'd1;
                end
                else begin
                    rx_rdy <= 1'd1;
                end
            end
        endcase
    end
end
endmodule