#! /c/Source/iverilog-install/bin/vvp :ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; :ivl_delay_selection "TYPICAL"; :vpi_time_precision - 12; :vpi_module "E:\iverilog\lib\ivl\system.vpi"; :vpi_module "E:\iverilog\lib\ivl\vhdl_sys.vpi"; :vpi_module "E:\iverilog\lib\ivl\vhdl_textio.vpi"; :vpi_module "E:\iverilog\lib\ivl\v2005_math.vpi"; :vpi_module "E:\iverilog\lib\ivl\va_math.vpi"; S_0000023cb4ac4680 .scope module, "clk_tb" "clk_tb" 2 4; .timescale -9 -12; v0000023cb4b52c10_0 .var "clk", 0 0; v0000023cb4b52f30_0 .net "clk_uart_tx", 0 0, v0000023cb4af37e0_0; 1 drivers v0000023cb4b51a90_0 .var "rst_n", 0 0; v0000023cb4b51450_0 .net "rx_data", 7 0, v0000023cb4af32e0_0; 1 drivers v0000023cb4b51810_0 .var "rx_pin", 0 0; v0000023cb4b51630_0 .net "rx_rdy", 0 0, v0000023cb4af31a0_0; 1 drivers v0000023cb4b52d50_0 .net "tx_busy", 0 0, v0000023cb4af3d80_0; 1 drivers v0000023cb4b51b30_0 .var "tx_data", 7 0; v0000023cb4b52cb0_0 .net "tx_pin", 0 0, v0000023cb4af3420_0; 1 drivers S_0000023cb4ade900 .scope module, "uart_top_inst" "uart_top" 2 37, 3 1 0, S_0000023cb4ac4680; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst_n"; .port_info 2 /OUTPUT 1 "clk_uart_tx"; .port_info 3 /OUTPUT 1 "tx_pin"; .port_info 4 /OUTPUT 1 "tx_busy"; .port_info 5 /INPUT 1 "rx_pin"; .port_info 6 /OUTPUT 8 "rx_data"; .port_info 7 /OUTPUT 1 "rx_rdy"; v0000023cb4b52b70_0 .net "clk", 0 0, v0000023cb4b52c10_0; 1 drivers v0000023cb4b51db0_0 .net "clk_uart_tx", 0 0, v0000023cb4af37e0_0; alias, 1 drivers v0000023cb4b52990_0 .net "rst_n", 0 0, v0000023cb4b51a90_0; 1 drivers v0000023cb4b528f0_0 .net "rx_data", 7 0, v0000023cb4af32e0_0; alias, 1 drivers v0000023cb4b52710_0 .net "rx_pin", 0 0, v0000023cb4b51810_0; 1 drivers v0000023cb4b52350_0 .net "rx_rdy", 0 0, v0000023cb4af31a0_0; alias, 1 drivers v0000023cb4b513b0_0 .var "send_data", 7 0; v0000023cb4b52e90_0 .var "send_flag", 0 0; v0000023cb4b52a30_0 .net "tx_busy", 0 0, v0000023cb4af3d80_0; alias, 1 drivers v0000023cb4b52ad0_0 .net "tx_pin", 0 0, v0000023cb4af3420_0; alias, 1 drivers E_0000023cb4ac11e0/0 .event negedge, v0000023cb4af3d80_0, v0000023cb4af3920_0; E_0000023cb4ac11e0/1 .event posedge, v0000023cb4af31a0_0; E_0000023cb4ac11e0 .event/or E_0000023cb4ac11e0/0, E_0000023cb4ac11e0/1; E_0000023cb4ac1c20/0 .event negedge, v0000023cb4af3920_0; E_0000023cb4ac1c20/1 .event posedge, v0000023cb4af31a0_0; E_0000023cb4ac1c20 .event/or E_0000023cb4ac1c20/0, E_0000023cb4ac1c20/1; S_0000023cb4adea90 .scope module, "uart_div_c0" "div_clk" 3 19, 4 1 0, S_0000023cb4ade900; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst_n"; .port_info 2 /OUTPUT 1 "clk_div"; P_0000023cb47a95a0 .param/l "COUNT_WITH" 0 4 4, +C4<00000000000000000000000000000110>; P_0000023cb47a95d8 .param/l "DIV" 0 4 3, C4<110010>; v0000023cb4af3a60_0 .net "clk", 0 0, v0000023cb4b52c10_0; alias, 1 drivers v0000023cb4af37e0_0 .var "clk_div", 0 0; v0000023cb4af3060_0 .var "count", 5 0; v0000023cb4af3920_0 .net "rst_n", 0 0, v0000023cb4b51a90_0; alias, 1 drivers E_0000023cb4ac1de0/0 .event negedge, v0000023cb4af3920_0; E_0000023cb4ac1de0/1 .event posedge, v0000023cb4af3a60_0; E_0000023cb4ac1de0 .event/or E_0000023cb4ac1de0/0, E_0000023cb4ac1de0/1; S_0000023cb4aeed70 .scope module, "uart_rx_c0" "uart_rx" 3 62, 5 1 0, S_0000023cb4ade900; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst_n"; .port_info 2 /INPUT 1 "rx_en"; .port_info 3 /INPUT 1 "rx"; .port_info 4 /OUTPUT 1 "rx_rdy"; .port_info 5 /OUTPUT 8 "rx_data"; P_0000023cb4ac4810 .param/l "DATA" 0 5 13, C4<10>; P_0000023cb4ac4848 .param/l "IDLE" 0 5 13, C4<01>; P_0000023cb4ac4880 .param/l "STOP" 0 5 13, C4<00>; v0000023cb4af3100_0 .net "clk", 0 0, v0000023cb4af37e0_0; alias, 1 drivers v0000023cb4af3600_0 .net "rst_n", 0 0, v0000023cb4b51a90_0; alias, 1 drivers v0000023cb4af3b00_0 .net "rx", 0 0, v0000023cb4b51810_0; alias, 1 drivers v0000023cb4af3ce0_0 .var "rx_cnt", 3 0; v0000023cb4af32e0_0 .var "rx_data", 7 0; L_0000023cb4ec00d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; v0000023cb4af3ba0_0 .net "rx_en", 0 0, L_0000023cb4ec00d0; 1 drivers v0000023cb4af31a0_0 .var "rx_rdy", 0 0; v0000023cb4af3240_0 .var "rx_reg", 7 0; v0000023cb4af3c40_0 .var "state", 1 0; E_0000023cb4ac1e20/0 .event negedge, v0000023cb4af3920_0; E_0000023cb4ac1e20/1 .event posedge, v0000023cb4af37e0_0; E_0000023cb4ac1e20 .event/or E_0000023cb4ac1e20/0, E_0000023cb4ac1e20/1; S_0000023cb4aeef00 .scope module, "uart_tx_c0" "uart_tx" 3 53, 6 1 0, S_0000023cb4ade900; .timescale 0 0; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst_n"; .port_info 2 /INPUT 1 "tx_en"; .port_info 3 /INPUT 1 "tx_start"; .port_info 4 /INPUT 8 "tx_data"; .port_info 5 /OUTPUT 1 "tx_busy"; .port_info 6 /OUTPUT 1 "tx_out"; P_0000023cb4abe7e0 .param/l "STA_DATA" 0 6 15, C4<10>; P_0000023cb4abe818 .param/l "STA_IDLE" 0 6 14, C4<01>; P_0000023cb4abe850 .param/l "STA_OFF" 0 6 13, C4<00>; v0000023cb4af34c0_0 .net "clk", 0 0, v0000023cb4af37e0_0; alias, 1 drivers v0000023cb4af3380_0 .var "cnt", 3 0; v0000023cb4af3560_0 .var "data", 7 0; v0000023cb4af3e20_0 .net "rst_n", 0 0, v0000023cb4b51a90_0; alias, 1 drivers v0000023cb4af3740_0 .var "state", 1 0; v0000023cb4af3d80_0 .var "tx_busy", 0 0; v0000023cb4af3ec0_0 .net "tx_data", 7 0, v0000023cb4b513b0_0; 1 drivers L_0000023cb4ec0088 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; v0000023cb4af2fc0_0 .net "tx_en", 0 0, L_0000023cb4ec0088; 1 drivers v0000023cb4af3420_0 .var "tx_out", 0 0; v0000023cb4af36a0_0 .net "tx_start", 0 0, v0000023cb4b52e90_0; 1 drivers E_0000023cb4ac22a0 .event anyedge, v0000023cb4af3740_0; .scope S_0000023cb4adea90; T_0 ; %wait E_0000023cb4ac1de0; %load/vec4 v0000023cb4af3920_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_0.0, 8; %pushi/vec4 0, 0, 6; %assign/vec4 v0000023cb4af3060_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4af37e0_0, 0; %jmp T_0.1; T_0.0 ; %load/vec4 v0000023cb4af3060_0; %pad/u 32; %cmpi/e 49, 0, 32; %jmp/0xz T_0.2, 4; %pushi/vec4 0, 0, 6; %assign/vec4 v0000023cb4af3060_0, 0; %load/vec4 v0000023cb4af37e0_0; %inv; %assign/vec4 v0000023cb4af37e0_0, 0; %jmp T_0.3; T_0.2 ; %load/vec4 v0000023cb4af3060_0; %addi 1, 0, 6; %assign/vec4 v0000023cb4af3060_0, 0; T_0.3 ; T_0.1 ; %jmp T_0; .thread T_0; .scope S_0000023cb4aeef00; T_1 ; %wait E_0000023cb4ac1e20; %load/vec4 v0000023cb4af3e20_0; %inv; %flag_set/vec4 8; %jmp/0xz T_1.0, 8; %pushi/vec4 0, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; %jmp T_1.1; T_1.0 ; %load/vec4 v0000023cb4af2fc0_0; %cmpi/e 1, 0, 1; %jmp/0xz T_1.2, 4; %load/vec4 v0000023cb4af3740_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_1.4, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_1.5, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_1.6, 6; %load/vec4 v0000023cb4af3740_0; %assign/vec4 v0000023cb4af3740_0, 0; %jmp T_1.8; T_1.4 ; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; %jmp T_1.8; T_1.5 ; %load/vec4 v0000023cb4af36a0_0; %cmpi/e 1, 0, 1; %jmp/0xz T_1.9, 4; %pushi/vec4 2, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; %jmp T_1.10; T_1.9 ; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; T_1.10 ; %jmp T_1.8; T_1.6 ; %load/vec4 v0000023cb4af3380_0; %cmpi/e 9, 0, 4; %jmp/0xz T_1.11, 4; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; %jmp T_1.12; T_1.11 ; %pushi/vec4 2, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; T_1.12 ; %jmp T_1.8; T_1.8 ; %pop/vec4 1; %jmp T_1.3; T_1.2 ; %pushi/vec4 0, 0, 2; %assign/vec4 v0000023cb4af3740_0, 0; T_1.3 ; T_1.1 ; %jmp T_1; .thread T_1; .scope S_0000023cb4aeef00; T_2 ; %wait E_0000023cb4ac22a0; %load/vec4 v0000023cb4af3740_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_2.0, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_2.1, 6; %load/vec4 v0000023cb4af3560_0; %assign/vec4 v0000023cb4af3560_0, 0; %jmp T_2.3; T_2.0 ; %pushi/vec4 0, 0, 8; %assign/vec4 v0000023cb4af3560_0, 0; %jmp T_2.3; T_2.1 ; %load/vec4 v0000023cb4af3ec0_0; %assign/vec4 v0000023cb4af3560_0, 0; %jmp T_2.3; T_2.3 ; %pop/vec4 1; %jmp T_2; .thread T_2, $push; .scope S_0000023cb4aeef00; T_3 ; %wait E_0000023cb4ac1e20; %load/vec4 v0000023cb4af3e20_0; %inv; %flag_set/vec4 8; %jmp/0xz T_3.0, 8; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4af3420_0, 0; %pushi/vec4 0, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %jmp T_3.1; T_3.0 ; %load/vec4 v0000023cb4af3740_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_3.2, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_3.3, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_3.4, 6; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4af3420_0, 0; %pushi/vec4 0, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %jmp T_3.6; T_3.2 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4af3420_0, 0; %pushi/vec4 0, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %jmp T_3.6; T_3.3 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4af3420_0, 0; %pushi/vec4 0, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %jmp T_3.6; T_3.4 ; %load/vec4 v0000023cb4af3380_0; %cmpi/e 0, 0, 4; %jmp/0xz T_3.7, 4; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4af3420_0, 0; %load/vec4 v0000023cb4af3380_0; %addi 1, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %jmp T_3.8; T_3.7 ; %load/vec4 v0000023cb4af3380_0; %cmpi/u 9, 0, 4; %jmp/0xz T_3.9, 5; %load/vec4 v0000023cb4af3560_0; %load/vec4 v0000023cb4af3380_0; %subi 1, 0, 4; %part/u 1; %assign/vec4 v0000023cb4af3420_0, 0; %load/vec4 v0000023cb4af3380_0; %addi 1, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %jmp T_3.10; T_3.9 ; %pushi/vec4 9, 0, 4; %assign/vec4 v0000023cb4af3380_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4af3420_0, 0; T_3.10 ; T_3.8 ; %jmp T_3.6; T_3.6 ; %pop/vec4 1; T_3.1 ; %jmp T_3; .thread T_3; .scope S_0000023cb4aeef00; T_4 ; %wait E_0000023cb4ac22a0; %load/vec4 v0000023cb4af3740_0; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_4.0, 6; %pushi/vec4 0, 0, 1; %store/vec4 v0000023cb4af3d80_0, 0, 1; %jmp T_4.2; T_4.0 ; %pushi/vec4 1, 0, 1; %store/vec4 v0000023cb4af3d80_0, 0, 1; %jmp T_4.2; T_4.2 ; %pop/vec4 1; %jmp T_4; .thread T_4, $push; .scope S_0000023cb4aeed70; T_5 ; %wait E_0000023cb4ac1e20; %load/vec4 v0000023cb4af3600_0; %inv; %flag_set/vec4 8; %jmp/0xz T_5.0, 8; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; %jmp T_5.1; T_5.0 ; %load/vec4 v0000023cb4af3ba0_0; %cmpi/e 0, 0, 1; %jmp/0xz T_5.2, 4; %pushi/vec4 0, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; %jmp T_5.3; T_5.2 ; %load/vec4 v0000023cb4af3c40_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_5.4, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_5.5, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_5.6, 6; %load/vec4 v0000023cb4af3c40_0; %assign/vec4 v0000023cb4af3c40_0, 0; %jmp T_5.8; T_5.4 ; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; %jmp T_5.8; T_5.5 ; %load/vec4 v0000023cb4af3b00_0; %cmpi/e 0, 0, 1; %jmp/0xz T_5.9, 4; %pushi/vec4 2, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; %jmp T_5.10; T_5.9 ; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; T_5.10 ; %jmp T_5.8; T_5.6 ; %load/vec4 v0000023cb4af3ce0_0; %cmpi/e 8, 0, 4; %jmp/0xz T_5.11, 4; %pushi/vec4 1, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; %jmp T_5.12; T_5.11 ; %pushi/vec4 2, 0, 2; %assign/vec4 v0000023cb4af3c40_0, 0; T_5.12 ; %jmp T_5.8; T_5.8 ; %pop/vec4 1; T_5.3 ; T_5.1 ; %jmp T_5; .thread T_5; .scope S_0000023cb4aeed70; T_6 ; %wait E_0000023cb4ac1e20; %load/vec4 v0000023cb4af3600_0; %inv; %flag_set/vec4 8; %jmp/0xz T_6.0, 8; %pushi/vec4 0, 0, 4; %assign/vec4 v0000023cb4af3ce0_0, 0; %pushi/vec4 0, 0, 8; %assign/vec4 v0000023cb4af3240_0, 0; %pushi/vec4 0, 0, 8; %assign/vec4 v0000023cb4af32e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4af31a0_0, 0; %jmp T_6.1; T_6.0 ; %load/vec4 v0000023cb4af3c40_0; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_6.2, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_6.3, 6; %load/vec4 v0000023cb4af3240_0; %assign/vec4 v0000023cb4af3240_0, 0; %load/vec4 v0000023cb4af3ce0_0; %assign/vec4 v0000023cb4af3ce0_0, 0; %load/vec4 v0000023cb4af32e0_0; %assign/vec4 v0000023cb4af32e0_0, 0; %load/vec4 v0000023cb4af31a0_0; %assign/vec4 v0000023cb4af31a0_0, 0; %jmp T_6.5; T_6.2 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0000023cb4af3ce0_0, 0; %pushi/vec4 0, 0, 8; %assign/vec4 v0000023cb4af3240_0, 0; %load/vec4 v0000023cb4af32e0_0; %assign/vec4 v0000023cb4af32e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4af31a0_0, 0; %jmp T_6.5; T_6.3 ; %load/vec4 v0000023cb4af3ce0_0; %cmpi/u 8, 0, 4; %jmp/0xz T_6.6, 5; %load/vec4 v0000023cb4af3b00_0; %ix/load 5, 0, 0; %ix/getv 4, v0000023cb4af3ce0_0; %assign/vec4/off/d v0000023cb4af3240_0, 4, 5; %load/vec4 v0000023cb4af3ce0_0; %addi 1, 0, 4; %assign/vec4 v0000023cb4af3ce0_0, 0; %jmp T_6.7; T_6.6 ; %load/vec4 v0000023cb4af3240_0; %assign/vec4 v0000023cb4af3240_0, 0; %load/vec4 v0000023cb4af3ce0_0; %assign/vec4 v0000023cb4af3ce0_0, 0; T_6.7 ; %load/vec4 v0000023cb4af3ce0_0; %cmpi/e 8, 0, 4; %jmp/0xz T_6.8, 4; %load/vec4 v0000023cb4af3240_0; %assign/vec4 v0000023cb4af32e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4af31a0_0, 0; %jmp T_6.9; T_6.8 ; %load/vec4 v0000023cb4af32e0_0; %assign/vec4 v0000023cb4af32e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4af31a0_0, 0; T_6.9 ; %jmp T_6.5; T_6.5 ; %pop/vec4 1; T_6.1 ; %jmp T_6; .thread T_6; .scope S_0000023cb4ade900; T_7 ; %wait E_0000023cb4ac1c20; %load/vec4 v0000023cb4b52990_0; %inv; %flag_set/vec4 8; %jmp/0xz T_7.0, 8; %pushi/vec4 0, 0, 8; %assign/vec4 v0000023cb4b513b0_0, 0; %jmp T_7.1; T_7.0 ; %load/vec4 v0000023cb4b528f0_0; %assign/vec4 v0000023cb4b513b0_0, 0; T_7.1 ; %jmp T_7; .thread T_7; .scope S_0000023cb4ade900; T_8 ; %wait E_0000023cb4ac11e0; %load/vec4 v0000023cb4b52990_0; %inv; %flag_set/vec4 8; %jmp/0xz T_8.0, 8; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4b52e90_0, 0; %jmp T_8.1; T_8.0 ; %load/vec4 v0000023cb4b52350_0; %cmpi/e 1, 0, 1; %jmp/0xz T_8.2, 4; %pushi/vec4 1, 0, 1; %assign/vec4 v0000023cb4b52e90_0, 0; %jmp T_8.3; T_8.2 ; %load/vec4 v0000023cb4b52a30_0; %cmpi/e 0, 0, 1; %jmp/0xz T_8.4, 4; %pushi/vec4 0, 0, 1; %assign/vec4 v0000023cb4b52e90_0, 0; %jmp T_8.5; T_8.4 ; %load/vec4 v0000023cb4b52e90_0; %assign/vec4 v0000023cb4b52e90_0, 0; T_8.5 ; T_8.3 ; T_8.1 ; %jmp T_8; .thread T_8; .scope S_0000023cb4ac4680; T_9 ; %pushi/vec4 0, 0, 1; %store/vec4 v0000023cb4b52c10_0, 0, 1; %end; .thread T_9; .scope S_0000023cb4ac4680; T_10 ; %delay 1000, 0; %load/vec4 v0000023cb4b52c10_0; %inv; %store/vec4 v0000023cb4b52c10_0, 0, 1; %jmp T_10; .thread T_10; .scope S_0000023cb4ac4680; T_11 ; %pushi/vec4 1, 0, 1; %store/vec4 v0000023cb4b51a90_0, 0, 1; %delay 1000, 0; %pushi/vec4 0, 0, 1; %store/vec4 v0000023cb4b51a90_0, 0, 1; %delay 1000, 0; %pushi/vec4 1, 0, 1; %store/vec4 v0000023cb4b51a90_0, 0, 1; %end; .thread T_11; .scope S_0000023cb4ac4680; T_12 ; %pushi/vec4 1, 0, 1; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 10000, 0; %pushi/vec4 85, 0, 8; %store/vec4 v0000023cb4b51b30_0, 0, 8; %pushi/vec4 0, 0, 1; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 0, 2; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 1, 2; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 2, 3; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 3, 3; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 4, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 5, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 6, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 7, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %pushi/vec4 1, 0, 1; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %pushi/vec4 170, 0, 8; %store/vec4 v0000023cb4b51b30_0, 0, 8; %pushi/vec4 0, 0, 1; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 0, 2; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 1, 2; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 2, 3; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 3, 3; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 4, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 5, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 6, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %load/vec4 v0000023cb4b51b30_0; %parti/s 1, 7, 4; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %pushi/vec4 1, 0, 1; %store/vec4 v0000023cb4b51810_0, 0, 1; %delay 200000, 0; %delay 200000, 0; %end; .thread T_12; .scope S_0000023cb4ac4680; T_13 ; %vpi_call 2 78 "$dumpfile", "uart_tb.vcd" {0 0 0}; %vpi_call 2 79 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000023cb4ac4680 {0 0 0}; %delay 100000000, 0; %vpi_call 2 80 "$finish" {0 0 0}; %end; .thread T_13; # The file index is used to find the file name in the following table. :file_names 7; "N/A"; ""; "uart_tb.v"; "uart_top.v"; "div_clk.v"; "uart_rx.v"; "uart_tx.v";