module uart_tx (
    input   wire        clk,
    input   wire        rst_n,
    input   wire        tx_en,
    input   wire        tx_start,
    input   wire [7:0]  tx_data,
    output  reg         uart_busy,
    output  reg         tx;
);


reg [7:0] tx_reg;
reg [4:0] tx_cnt;

always @(posedge clk or negedge rst_n or posedge tx_start) begin
    if (~rst_n) begin
       tx <= 1'b1;
       tx_reg <= 8'd0;
       tx_cnt <= 5'd0;
       uart_busy <= 1'b0;
    end 
    else if(tx_start) begin
        if(tx_cnt == 0) begin
            tx_reg <= tx_data;
            tx_cnt <= 4'd10;
            uart_busy <= 1'b1;
        end
        else begin
            tx_cnt <= tx_cnt;
        end
    end

    else begin
        if(tx_cnt > 0) begin
            if(tx_cnt == 4'd10) begin
                tx <= 1'b0;
            end 
            else if(tx_cnt > 4'd1) begin
                tx <= tx_reg[0];
                tx_reg <= tx_reg >> 1;
            end
            else  begin
                tx <= 1'b1;
                
            end
            tx_cnt <= tx_cnt - 1;
        end
        else begin
            tx_cnt <= tx_cnt;
            tx <= 1'b1;
            uart_busy <= 1'b0;
        end
    end
end


endmodule //uart_tx