module test_top (
    input  wire clk,
    input  wire rst_n,
    output wire a2,
    output wire a3,
    output wire a4,
    output wire a5,
    output wire a6,
    output wire a7,
    output wire a8,
    output wire a9
);

wire clk_low;
div_clk #(
    .COUNT_WITH(10),
    .DIV(50)
) div_clk_inst (
    .clk(clk),
    .rst_n(rst_n),
    .clk_div(clk_low),
);
assign a2 = data[0];
assign a3 = data[1];
assign a4 = data[2];
assign a5 = data[3];
assign a6 = data[4];
assign a7 = data[5];
assign a8 = data[6];
assign a9 = data[7];
reg [7:0] data;
always @(posedge clk_low or negedge rst_n) begin
    if (!rst_n) begin
        data <= 8'd0;
    end
    else begin
        data <= data + 1'b1;
    end
end
endmodule //test_top