module test_top (
    input  wire clk,
    input  wire rst_n,
    output reg a2,
    output reg a3,
    output reg a4,
    output reg a5,
    output reg a6,
    output reg a7,
    output reg a8,
    output reg a9
);

wire clk_low;
div_clk #(
    .COUNT_WITH(10),
    .DIV(50)
) div_clk_inst (
    .clk(clk),
    .rst_n(rst_n),
    .clk_div(clk_low)
);

reg [7:0] data;
always @(posedge clk_low or negedge rst_n) begin
    if (!rst_n) begin
        data <= 8'd0;
        a2 <= 1'b0;
        a3 <= 1'b0;
        a4 <= 1'b0;
        a5 <= 1'b0;
        a6 <= 1'b0; 
        a7 <= 1'b0;
        a8 <= 1'b0;
        a9 <= 1'b0;
    end
    else begin
        a2 <= data[0];
        a3 <= data[1];
        a4 <= data[2];
        a5 <= data[3];
        a6 <= data[4];
        a7 <= data[5];
        a8 <= data[6];
        a9 <= data[7];
        data <= data + 1'b1;
    end
end
endmodule //test_top