`timescale 1ns/1ps


module clk_tb;

reg clk, rst_n;

initial begin
    clk = 0;
end

always #5 clk = ~clk;


initial begin
    rst_n = 1;
    #10 rst_n = 0;
    #10 rst_n = 1;
end

clk_test tb_clk(
    .clk(clk),
    .rst_n(rst)
);

initial begin
    $dumpfile("clk_tb.vcd");
    $dumpvars(0, clk_tb);
    #1000 $finish;
end


endmodule