This commit is contained in:
parent
d15f011b4b
commit
0864208bd6
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@ -1,3 +0,0 @@
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[submodule "fpga2"]
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path = fpga2
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url = http://chenyf123.top:1030/FPGA_util/fpga2.git
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@ -1,230 +0,0 @@
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#include <windows.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define BUILD_DIR ".\\build"
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#define GITREV_FILE ".\\build\\gitrev.txt"
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#define GITHASH_FILE ".\\build\\githash.txt"
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#define GITSTATUS_FILE ".\\build\\gitstatus.txt"
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#define REVISION_H_FILE "..\\applications\\revision.h"
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void createBuildDir()
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{
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if (!CreateDirectory(BUILD_DIR, NULL))
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{
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if (GetLastError() != ERROR_ALREADY_EXISTS)
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{
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printf("Failed to create build directory.\n");
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exit(EXIT_FAILURE);
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}
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}
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}
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void deleteRevisionH()
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{
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if (!DeleteFile(REVISION_H_FILE))
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{
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printf("Failed to delete revision.h.\n");
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// exit(EXIT_FAILURE);
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}
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}
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int find_git_revision_number()
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{
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FILE *fp = popen("git rev-list HEAD", "r");
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if (fp == NULL)
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{
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perror("popen failed");
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return EXIT_FAILURE;
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}
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int cnt = 0;
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char buffer[1024];
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while (fgets(buffer, sizeof(buffer), fp) != NULL)
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{
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// printf("%s", buffer);
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cnt++;
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}
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pclose(fp);
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return cnt;
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}
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int get_latest_version_hash(char *buffer, int len)
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{
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FILE *fp = popen("git rev-list HEAD", "r");
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if (fp == NULL)
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{
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perror("popen failed");
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return EXIT_FAILURE;
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}
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int cnt = 0;
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while (fgets(buffer, len, fp) != NULL)
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{
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}
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pclose(fp);
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return cnt;
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}
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/**
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*
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*
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*
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*/
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int get_git_state()
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{
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FILE *fp = popen("git status", "r");
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if (fp == NULL)
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{
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perror("popen failed");
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return EXIT_FAILURE;
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}
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char buffer[1024];
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while (fgets(buffer, sizeof(buffer), fp) != NULL)
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{
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printf("%s\n", buffer);
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if (strstr(buffer, "modified:") != NULL)
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{
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return 'M';
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}
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if (strstr(buffer, "new file") != NULL)
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{
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return 'N';
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}
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if (strstr(buffer, "deleted:") != NULL)
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{
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return 'D';
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}
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if (strstr(buffer, "renamed:") != NULL)
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{
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return 'R';
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}
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}
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pclose(fp);
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return '\0';
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}
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int write_notargeted_file(int version_number, char *version_hash, char sta)
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{
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FILE *fp = fopen(REVISION_H_FILE, "w+");
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if (fp == NULL)
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{
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perror("fopen failed");
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return EXIT_FAILURE;
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}
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fprintf(fp, "#ifndef REVISION_H_\n");
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fprintf(fp, "#define REVISION_H_\n");
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fprintf(fp, "#define FIRMWARE_VER_REV %d\n", version_number);
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fprintf(fp, "#define FIRMWARE_VER_REV_STR \"%d\"\n", version_number);
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fprintf(fp, "#define FIRMWARE_VER_HASH_STR ");
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fprintf(fp, "\"");
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for (int i = 0; i < 8; i++)
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{
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fprintf(fp, "%c", version_hash[i]);
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}
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fprintf(fp, "\"");
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fprintf(fp, "\n");
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fprintf(fp, "#define FIRMWARE_VER_MULTI \"%c\"\n", sta);
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fprintf(fp, "#define FIRMWARE_BUILD_INFO \"r\"FIRMWARE_VER_REV_STR\" built on \"__DATE__\" \"__TIME__\n");
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fprintf(fp, "#endif // REVISION_H_\n");
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fclose(fp);
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return 0;
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}
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int print_git_submodule_info(FILE *fp_write)
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{
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FILE *fp = popen("git submodule status --recursive", "r");
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if (fp == NULL)
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{
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perror("popen failed");
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return EXIT_FAILURE;
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}
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char buffer[1024];
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fprintf(fp_write, "\"\\\n");
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while (fgets(buffer, 1024, fp) != NULL)
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{
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char *pos = buffer;
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while (*pos != '\0' && *pos != '\r' && *pos != '\n')
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{
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fprintf(fp_write, "%c", *pos);
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pos++;
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}
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fprintf(fp_write, " \\r\\n\\\n");
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}
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fprintf(fp_write, "\"\n");
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pclose(fp);
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}
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int write_targeted_file(int version_number, char *version_hash, char sta)
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{
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FILE *fp = fopen(REVISION_H_FILE, "w+");
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if (fp == NULL)
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{
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perror("fopen failed");
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return EXIT_FAILURE;
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}
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fprintf(fp, "#ifndef REVISION_H_\n");
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fprintf(fp, "#define REVISION_H_\n");
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fprintf(fp, "#if (defined DEBUG)\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"debug\"\n");
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fprintf(fp, "#elif (defined _DEBUG)\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"debug\"\n");
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fprintf(fp, "#elif (defined __DEBUG)\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"debug\"\n");
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fprintf(fp, "#elif (defined DISTRIBUTION)\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"distribution\"\n");
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fprintf(fp, "#elif (defined _DISTRIBUTION)\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"distribution\"\n");
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fprintf(fp, "#elif (defined __DISTRIBUTION)\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"distribution\"\n");
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fprintf(fp, "#else\n");
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fprintf(fp, "#define FIRMWARE_TARGET_STR \"release\"\n");
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fprintf(fp, "#endif\n");
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fprintf(fp, "#define FIRMWARE_VER_REV %d\n", version_number);
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fprintf(fp, "#define FIRMWARE_VER_REV_STR \"%d\"\n", version_number);
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fprintf(fp, "#define FIRMWARE_VER_HASH_STR ");
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fprintf(fp, "\"");
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for (int i = 0; i < 8; i++)
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{
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fprintf(fp, "%c", version_hash[i]);
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}
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fprintf(fp, "\"");
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fprintf(fp, "\n");
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if (sta == '\0')
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{
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fprintf(fp, "#define FIRMWARE_VER_MULTI \"\"\n");
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fprintf(fp, "#define FIRMWARE_BUILD_INFO \"r\"FIRMWARE_VER_REV_STR\"-\"FIRMWARE_VER_HASH_STR\" \"FIRMWARE_TARGET_STR\" \"\" built on \"__DATE__\" \"__TIME__\n");
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}
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else
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{
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fprintf(fp, "#define FIRMWARE_VER_MULTI \"%c\"\n", sta);
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fprintf(fp, "#define FIRMWARE_BUILD_INFO \"r\"FIRMWARE_VER_REV_STR\"-\"FIRMWARE_VER_HASH_STR\"-\"FIRMWARE_VER_MULTI\" \"FIRMWARE_TARGET_STR\" \"\" built on \"__DATE__\" \"__TIME__\n");
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}
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fprintf(fp, "#define FIRMWARE_SUBMODULE_REV \\\n");
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print_git_submodule_info(fp);
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fprintf(fp, "#endif\n");
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return 0;
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}
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int main(int argc, char **argv)
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{
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createBuildDir();
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// deleteRevisionH();
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int version_number = find_git_revision_number();
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char version_hash[256];
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get_latest_version_hash(version_hash, sizeof(version_hash));
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printf("%s\n", version_hash);
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char sta = get_git_state();
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printf("git state is : %c\n", sta);
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if (argv[2][0] != 's')
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{
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write_notargeted_file(version_number, version_hash, sta);
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}
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else
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{
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write_targeted_file(version_number, version_hash, sta);
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}
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return 0;
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}
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Binary file not shown.
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@ -0,0 +1,2 @@
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iverilog -o out clk_test.v clk_tb.v
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vvp out
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@ -0,0 +1,33 @@
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`timescale 1ns/1ps
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module clk_tb;
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reg clk, rst_n;
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initial begin
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clk = 0;
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end
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always #5 clk = ~clk;
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initial begin
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rst_n = 1;
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#10 rst_n = 0;
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#10 rst_n = 1;
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end
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clk_test tb_clk(
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.clk(clk),
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.rst_n(rst)
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|
);
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|
initial begin
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|
$dumpfile("clk_tb.vcd");
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|
$dumpvars(0, clk_tb);
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|
#1000 $finish;
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|
end
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endmodule
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@ -0,0 +1,532 @@
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$date
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|
Tue Jul 30 20:27:09 2024
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|
$end
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|
$version
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|
Icarus Verilog
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|
$end
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||||||
|
$timescale
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|
1ps
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|
$end
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||||||
|
$scope module clk_tb $end
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|
$var wire 1 ! rst $end
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|
$var reg 1 " clk $end
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|
$var reg 1 # rst_n $end
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|
$scope module tb_clk $end
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|
$var wire 1 " clk $end
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|
$var wire 1 ! rst_n $end
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|
$var reg 1 $ clk_out $end
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||||||
|
$upscope $end
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||||||
|
$upscope $end
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||||||
|
$enddefinitions $end
|
||||||
|
$comment Show the parameter values. $end
|
||||||
|
$dumpall
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||||||
|
$end
|
||||||
|
#0
|
||||||
|
$dumpvars
|
||||||
|
x$
|
||||||
|
1#
|
||||||
|
0"
|
||||||
|
z!
|
||||||
|
$end
|
||||||
|
#5000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#10000
|
||||||
|
0"
|
||||||
|
0#
|
||||||
|
#15000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#20000
|
||||||
|
0"
|
||||||
|
1#
|
||||||
|
#25000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#30000
|
||||||
|
0"
|
||||||
|
#35000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#40000
|
||||||
|
0"
|
||||||
|
#45000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#50000
|
||||||
|
0"
|
||||||
|
#55000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#60000
|
||||||
|
0"
|
||||||
|
#65000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#70000
|
||||||
|
0"
|
||||||
|
#75000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#80000
|
||||||
|
0"
|
||||||
|
#85000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#90000
|
||||||
|
0"
|
||||||
|
#95000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#100000
|
||||||
|
0"
|
||||||
|
#105000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#110000
|
||||||
|
0"
|
||||||
|
#115000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#120000
|
||||||
|
0"
|
||||||
|
#125000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#130000
|
||||||
|
0"
|
||||||
|
#135000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#140000
|
||||||
|
0"
|
||||||
|
#145000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#150000
|
||||||
|
0"
|
||||||
|
#155000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#160000
|
||||||
|
0"
|
||||||
|
#165000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#170000
|
||||||
|
0"
|
||||||
|
#175000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#180000
|
||||||
|
0"
|
||||||
|
#185000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#190000
|
||||||
|
0"
|
||||||
|
#195000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#200000
|
||||||
|
0"
|
||||||
|
#205000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#210000
|
||||||
|
0"
|
||||||
|
#215000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#220000
|
||||||
|
0"
|
||||||
|
#225000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#230000
|
||||||
|
0"
|
||||||
|
#235000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#240000
|
||||||
|
0"
|
||||||
|
#245000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#250000
|
||||||
|
0"
|
||||||
|
#255000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#260000
|
||||||
|
0"
|
||||||
|
#265000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#270000
|
||||||
|
0"
|
||||||
|
#275000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#280000
|
||||||
|
0"
|
||||||
|
#285000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#290000
|
||||||
|
0"
|
||||||
|
#295000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#300000
|
||||||
|
0"
|
||||||
|
#305000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#310000
|
||||||
|
0"
|
||||||
|
#315000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#320000
|
||||||
|
0"
|
||||||
|
#325000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#330000
|
||||||
|
0"
|
||||||
|
#335000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#340000
|
||||||
|
0"
|
||||||
|
#345000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#350000
|
||||||
|
0"
|
||||||
|
#355000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#360000
|
||||||
|
0"
|
||||||
|
#365000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#370000
|
||||||
|
0"
|
||||||
|
#375000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#380000
|
||||||
|
0"
|
||||||
|
#385000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#390000
|
||||||
|
0"
|
||||||
|
#395000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#400000
|
||||||
|
0"
|
||||||
|
#405000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#410000
|
||||||
|
0"
|
||||||
|
#415000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#420000
|
||||||
|
0"
|
||||||
|
#425000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#430000
|
||||||
|
0"
|
||||||
|
#435000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#440000
|
||||||
|
0"
|
||||||
|
#445000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#450000
|
||||||
|
0"
|
||||||
|
#455000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#460000
|
||||||
|
0"
|
||||||
|
#465000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#470000
|
||||||
|
0"
|
||||||
|
#475000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#480000
|
||||||
|
0"
|
||||||
|
#485000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#490000
|
||||||
|
0"
|
||||||
|
#495000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#500000
|
||||||
|
0"
|
||||||
|
#505000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#510000
|
||||||
|
0"
|
||||||
|
#515000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#520000
|
||||||
|
0"
|
||||||
|
#525000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#530000
|
||||||
|
0"
|
||||||
|
#535000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#540000
|
||||||
|
0"
|
||||||
|
#545000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#550000
|
||||||
|
0"
|
||||||
|
#555000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#560000
|
||||||
|
0"
|
||||||
|
#565000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#570000
|
||||||
|
0"
|
||||||
|
#575000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#580000
|
||||||
|
0"
|
||||||
|
#585000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#590000
|
||||||
|
0"
|
||||||
|
#595000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#600000
|
||||||
|
0"
|
||||||
|
#605000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#610000
|
||||||
|
0"
|
||||||
|
#615000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#620000
|
||||||
|
0"
|
||||||
|
#625000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#630000
|
||||||
|
0"
|
||||||
|
#635000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#640000
|
||||||
|
0"
|
||||||
|
#645000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#650000
|
||||||
|
0"
|
||||||
|
#655000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#660000
|
||||||
|
0"
|
||||||
|
#665000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#670000
|
||||||
|
0"
|
||||||
|
#675000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#680000
|
||||||
|
0"
|
||||||
|
#685000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#690000
|
||||||
|
0"
|
||||||
|
#695000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#700000
|
||||||
|
0"
|
||||||
|
#705000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#710000
|
||||||
|
0"
|
||||||
|
#715000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#720000
|
||||||
|
0"
|
||||||
|
#725000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#730000
|
||||||
|
0"
|
||||||
|
#735000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#740000
|
||||||
|
0"
|
||||||
|
#745000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#750000
|
||||||
|
0"
|
||||||
|
#755000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#760000
|
||||||
|
0"
|
||||||
|
#765000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#770000
|
||||||
|
0"
|
||||||
|
#775000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#780000
|
||||||
|
0"
|
||||||
|
#785000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#790000
|
||||||
|
0"
|
||||||
|
#795000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#800000
|
||||||
|
0"
|
||||||
|
#805000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#810000
|
||||||
|
0"
|
||||||
|
#815000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#820000
|
||||||
|
0"
|
||||||
|
#825000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#830000
|
||||||
|
0"
|
||||||
|
#835000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#840000
|
||||||
|
0"
|
||||||
|
#845000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#850000
|
||||||
|
0"
|
||||||
|
#855000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#860000
|
||||||
|
0"
|
||||||
|
#865000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#870000
|
||||||
|
0"
|
||||||
|
#875000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#880000
|
||||||
|
0"
|
||||||
|
#885000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#890000
|
||||||
|
0"
|
||||||
|
#895000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#900000
|
||||||
|
0"
|
||||||
|
#905000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#910000
|
||||||
|
0"
|
||||||
|
#915000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#920000
|
||||||
|
0"
|
||||||
|
#925000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#930000
|
||||||
|
0"
|
||||||
|
#935000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#940000
|
||||||
|
0"
|
||||||
|
#945000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#950000
|
||||||
|
0"
|
||||||
|
#955000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#960000
|
||||||
|
0"
|
||||||
|
#965000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#970000
|
||||||
|
0"
|
||||||
|
#975000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#980000
|
||||||
|
0"
|
||||||
|
#985000
|
||||||
|
0$
|
||||||
|
1"
|
||||||
|
#990000
|
||||||
|
0"
|
||||||
|
#995000
|
||||||
|
1$
|
||||||
|
1"
|
||||||
|
#1000000
|
||||||
|
0"
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
module clk_test (
|
||||||
|
input wire clk,
|
||||||
|
input wire rst_n
|
||||||
|
);
|
||||||
|
|
||||||
|
reg clk_out;
|
||||||
|
|
||||||
|
|
||||||
|
always @(posedge clk or negedge rst_n) begin
|
||||||
|
if (!rst_n) begin
|
||||||
|
clk_out <= 0;
|
||||||
|
end else begin
|
||||||
|
if (clk_out == 1'b0) begin
|
||||||
|
clk_out <= 1'b1;
|
||||||
|
end else begin
|
||||||
|
clk_out <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
endmodule //clk_test
|
||||||
|
|
@ -0,0 +1,89 @@
|
||||||
|
#! /c/Source/iverilog-install/bin/vvp
|
||||||
|
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||||
|
:ivl_delay_selection "TYPICAL";
|
||||||
|
:vpi_time_precision - 12;
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\system.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\v2005_math.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\va_math.vpi";
|
||||||
|
S_0000029dbbc06940 .scope module, "clk_tb" "clk_tb" 2 4;
|
||||||
|
.timescale -9 -12;
|
||||||
|
v0000029dbbbbb840_0 .var "clk", 0 0;
|
||||||
|
o0000029dbbc07038 .functor BUFZ 1, C4<z>; HiZ drive
|
||||||
|
v0000029dbbbbb8e0_0 .net "rst", 0 0, o0000029dbbc07038; 0 drivers
|
||||||
|
v0000029dbbbbb980_0 .var "rst_n", 0 0;
|
||||||
|
S_0000029dbbc06ad0 .scope module, "tb_clk" "clk_test" 2 21, 3 1 0, S_0000029dbbc06940;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "clk";
|
||||||
|
.port_info 1 /INPUT 1 "rst_n";
|
||||||
|
v0000029dbbbd32c0_0 .net "clk", 0 0, v0000029dbbbbb840_0; 1 drivers
|
||||||
|
v0000029dbbbd2bf0_0 .var "clk_out", 0 0;
|
||||||
|
v0000029dbbbd3090_0 .net "rst_n", 0 0, o0000029dbbc07038; alias, 0 drivers
|
||||||
|
E_0000029dbbbbd100/0 .event negedge, v0000029dbbbd3090_0;
|
||||||
|
E_0000029dbbbbd100/1 .event posedge, v0000029dbbbd32c0_0;
|
||||||
|
E_0000029dbbbbd100 .event/or E_0000029dbbbbd100/0, E_0000029dbbbbd100/1;
|
||||||
|
.scope S_0000029dbbc06ad0;
|
||||||
|
T_0 ;
|
||||||
|
%wait E_0000029dbbbbd100;
|
||||||
|
%load/vec4 v0000029dbbbd3090_0;
|
||||||
|
%nor/r;
|
||||||
|
%flag_set/vec4 8;
|
||||||
|
%jmp/0xz T_0.0, 8;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0000029dbbbd2bf0_0, 0;
|
||||||
|
%jmp T_0.1;
|
||||||
|
T_0.0 ;
|
||||||
|
%load/vec4 v0000029dbbbd2bf0_0;
|
||||||
|
%cmpi/e 0, 0, 1;
|
||||||
|
%jmp/0xz T_0.2, 4;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%assign/vec4 v0000029dbbbd2bf0_0, 0;
|
||||||
|
%jmp T_0.3;
|
||||||
|
T_0.2 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0000029dbbbd2bf0_0, 0;
|
||||||
|
T_0.3 ;
|
||||||
|
T_0.1 ;
|
||||||
|
%jmp T_0;
|
||||||
|
.thread T_0;
|
||||||
|
.scope S_0000029dbbc06940;
|
||||||
|
T_1 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0000029dbbbbb840_0, 0, 1;
|
||||||
|
%end;
|
||||||
|
.thread T_1;
|
||||||
|
.scope S_0000029dbbc06940;
|
||||||
|
T_2 ;
|
||||||
|
%delay 5000, 0;
|
||||||
|
%load/vec4 v0000029dbbbbb840_0;
|
||||||
|
%inv;
|
||||||
|
%store/vec4 v0000029dbbbbb840_0, 0, 1;
|
||||||
|
%jmp T_2;
|
||||||
|
.thread T_2;
|
||||||
|
.scope S_0000029dbbc06940;
|
||||||
|
T_3 ;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0000029dbbbbb980_0, 0, 1;
|
||||||
|
%delay 10000, 0;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0000029dbbbbb980_0, 0, 1;
|
||||||
|
%delay 10000, 0;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0000029dbbbbb980_0, 0, 1;
|
||||||
|
%end;
|
||||||
|
.thread T_3;
|
||||||
|
.scope S_0000029dbbc06940;
|
||||||
|
T_4 ;
|
||||||
|
%vpi_call 2 27 "$dumpfile", "clk_tb.vcd" {0 0 0};
|
||||||
|
%vpi_call 2 28 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000029dbbc06940 {0 0 0};
|
||||||
|
%delay 1000000, 0;
|
||||||
|
%vpi_call 2 29 "$finish" {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_4;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 4;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"clk_tb.v";
|
||||||
|
"clk_test.v";
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
#! /c/Source/iverilog-install/bin/vvp
|
||||||
|
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||||
|
:ivl_delay_selection "TYPICAL";
|
||||||
|
:vpi_time_precision - 12;
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\system.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\v2005_math.vpi";
|
||||||
|
:vpi_module "E:\iverilog\lib\ivl\va_math.vpi";
|
||||||
|
S_0000022e5e572830 .scope module, "clk_tb" "clk_tb" 2 4;
|
||||||
|
.timescale -9 -12;
|
||||||
|
v0000022e5e5729c0_0 .var "clk", 0 0;
|
||||||
|
v0000022e5e572a60_0 .var "rst", 0 0;
|
||||||
|
.scope S_0000022e5e572830;
|
||||||
|
T_0 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0000022e5e5729c0_0, 0, 1;
|
||||||
|
%end;
|
||||||
|
.thread T_0;
|
||||||
|
.scope S_0000022e5e572830;
|
||||||
|
T_1 ;
|
||||||
|
%delay 5000, 0;
|
||||||
|
%load/vec4 v0000022e5e5729c0_0;
|
||||||
|
%inv;
|
||||||
|
%store/vec4 v0000022e5e5729c0_0, 0, 1;
|
||||||
|
%jmp T_1;
|
||||||
|
.thread T_1;
|
||||||
|
.scope S_0000022e5e572830;
|
||||||
|
T_2 ;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%store/vec4 v0000022e5e572a60_0, 0, 1;
|
||||||
|
%delay 10000, 0;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0000022e5e572a60_0, 0, 1;
|
||||||
|
%end;
|
||||||
|
.thread T_2;
|
||||||
|
.scope S_0000022e5e572830;
|
||||||
|
T_3 ;
|
||||||
|
%vpi_call 2 22 "$dumpfile", "clk_tb.vcd" {0 0 0};
|
||||||
|
%vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000022e5e572830 {0 0 0};
|
||||||
|
%delay 1000000, 0;
|
||||||
|
%vpi_call 2 24 "$finish" {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_3;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 3;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"clk_tb.v";
|
||||||
1
fpga2
1
fpga2
|
|
@ -1 +0,0 @@
|
||||||
Subproject commit 0cdca8460daa2167a6d49f247034f2c8cb888c6d
|
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
module div_clk(input clk, rst_n, output reg clk_div);
|
||||||
|
|
||||||
|
parameter DIV = 10;
|
||||||
|
parameter COUNT_WITH = 10;
|
||||||
|
reg [COUNT_WITH-1:0] count;
|
||||||
|
|
||||||
|
always @(posedge clk or negedge rst_n) begin
|
||||||
|
if (!rst_n) begin
|
||||||
|
count <= 0;
|
||||||
|
clk_div <= 0;
|
||||||
|
end else begin
|
||||||
|
if (count == (DIV-1)) begin
|
||||||
|
count <= 0;
|
||||||
|
clk_div <= ~clk_div;
|
||||||
|
end else begin
|
||||||
|
count <= count + 1'd1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,112 @@
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1722615779409 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615779409 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:22:59 2024 " "Processing started: Sat Aug 03 00:22:59 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615779409 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1722615779409 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1722615779409 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1722615779765 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/test/test_top.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/test/test_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_top " "Found entity 1: test_top" { } { { "../test_top.v" "" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722615779807 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722615779807 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/test/div_clk.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/test/div_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_clk " "Found entity 1: div_clk" { } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/test/div_clk.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722615779808 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722615779808 ""}
|
||||||
|
{ "Info" "ISGN_START_ELABORATION_TOP" "test_top " "Elaborating entity \"test_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1722615779832 ""}
|
||||||
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_clk div_clk:div_clk_inst " "Elaborating entity \"div_clk\" for hierarchy \"div_clk:div_clk_inst\"" { } { { "../test_top.v" "div_clk_inst" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 22 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1722615779840 ""}
|
||||||
|
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1722615780190 ""}
|
||||||
|
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1722615780347 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1722615780347 ""}
|
||||||
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1722615780367 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1722615780367 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1722615780367 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1722615780367 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615780385 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:23:00 2024 " "Processing ended: Sat Aug 03 00:23:00 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615780385 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615780385 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615780385 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1722615780385 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1722615781678 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615781679 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:23:01 2024 " "Processing started: Sat Aug 03 00:23:01 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615781679 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1722615781679 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off test -c test " "Command: quartus_fit --read_settings_files=off --write_settings_files=off test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1722615781679 ""}
|
||||||
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1722615781773 ""}
|
||||||
|
{ "Info" "0" "" "Project = test" { } { } 0 0 "Project = test" 0 0 "Fitter" 0 0 1722615781773 ""}
|
||||||
|
{ "Info" "0" "" "Revision = test" { } { } 0 0 "Revision = test" 0 0 "Fitter" 0 0 1722615781773 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1722615781818 ""}
|
||||||
|
{ "Info" "IMPP_MPP_USER_DEVICE" "test EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1722615781829 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722615781863 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722615781863 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722615781864 ""}
|
||||||
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1722615781917 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722615782140 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722615782140 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722615782140 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1722615782140 ""}
|
||||||
|
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 60 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615782141 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 62 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615782141 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 64 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615782141 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 66 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615782141 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 68 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615782141 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1722615782141 ""}
|
||||||
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1722615782142 ""}
|
||||||
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1722615782653 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1722615782653 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1722615782654 ""}
|
||||||
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1722615782654 ""}
|
||||||
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1722615782654 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722615782659 ""} } { { "../test_top.v" "" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 2 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 54 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722615782659 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node rst_n~input (placed in PIN M1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722615782659 ""} } { { "../test_top.v" "" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 3 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rst_n~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 55 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722615782659 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1722615782851 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1722615782852 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1722615782852 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1722615782852 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1722615782852 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1722615782852 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1722615782853 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1722615782853 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1722615782862 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1722615782862 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1722615782862 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615782870 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1722615783258 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615783294 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1722615783300 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1722615783635 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615783635 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1722615783834 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y12 X10_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24" { } { { "loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24"} 0 12 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1722615784072 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1722615784072 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615784207 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1722615784207 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1722615784207 ""}
|
||||||
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.19 " "Total time spent on timing analysis during the Fitter is 0.19 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1722615784213 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1722615784260 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1722615784376 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1722615784419 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1722615784539 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615784805 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/FPGA_lib/test/par/output_files/test.fit.smsg " "Generated suppressed messages file E:/FPGA/FPGA_lib/test/par/output_files/test.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1722615785117 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5869 " "Peak virtual memory: 5869 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615785341 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:23:05 2024 " "Processing ended: Sat Aug 03 00:23:05 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615785341 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615785341 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615785341 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1722615785341 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1722615786460 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615786460 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:23:06 2024 " "Processing started: Sat Aug 03 00:23:06 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615786460 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1722615786460 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off test -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1722615786460 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1722615786963 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1722615786976 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4590 " "Peak virtual memory: 4590 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615787229 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:23:07 2024 " "Processing ended: Sat Aug 03 00:23:07 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615787229 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615787229 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615787229 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1722615787229 ""}
|
||||||
|
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1722615787916 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1722615788640 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615788641 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:23:08 2024 " "Processing started: Sat Aug 03 00:23:08 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615788641 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1722615788641 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta test -c test " "Command: quartus_sta test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1722615788641 ""}
|
||||||
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1722615788742 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1722615788916 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1722615788916 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1722615788950 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1722615788950 ""}
|
||||||
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1722615789116 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1722615789116 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789116 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789116 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1722615789184 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789184 ""}
|
||||||
|
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1722615789185 ""}
|
||||||
|
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1722615789189 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1722615789195 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1722615789195 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.227 " "Worst-case setup slack is -1.227" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789197 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789197 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.227 -8.712 clk " " -1.227 -8.712 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789197 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789197 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.464 " "Worst-case hold slack is 0.464" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.464 0.000 clk " " 0.464 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789199 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789199 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615789201 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615789202 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789204 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789204 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -26.792 clk " " -3.000 -26.792 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789204 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789204 ""}
|
||||||
|
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1722615789219 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1722615789237 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1722615789427 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789462 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1722615789466 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1722615789466 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.015 " "Worst-case setup slack is -1.015" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789467 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789467 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.015 -6.646 clk " " -1.015 -6.646 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789467 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789467 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.416 " "Worst-case hold slack is 0.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.416 0.000 clk " " 0.416 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789469 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789469 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615789471 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615789473 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -26.792 clk " " -3.000 -26.792 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789475 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789475 ""}
|
||||||
|
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1722615789490 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789621 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.042 " "Worst-case setup slack is 0.042" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789624 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789624 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.042 0.000 clk " " 0.042 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789624 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789624 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.189 " "Worst-case hold slack is 0.189" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789627 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789627 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.189 0.000 clk " " 0.189 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789627 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789627 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615789629 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615789632 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1722615789632 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1722615789632 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -20.018 clk " " -3.000 -20.018 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615789634 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615789634 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1722615789907 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1722615789907 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4754 " "Peak virtual memory: 4754 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615789948 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:23:09 2024 " "Processing ended: Sat Aug 03 00:23:09 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615789948 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615789948 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615789948 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1722615789948 ""}
|
||||||
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 6 s " "Quartus II Full Compilation was successful. 0 errors, 6 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1722615790557 ""}
|
||||||
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|
@ -0,0 +1,6 @@
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1722615858344 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615858345 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:24:18 2024 " "Processing started: Sat Aug 03 00:24:18 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615858345 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1722615858345 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off test -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1722615858345 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1722615858848 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1722615858861 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4590 " "Peak virtual memory: 4590 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615859128 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:24:19 2024 " "Processing ended: Sat Aug 03 00:24:19 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615859128 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615859128 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615859128 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1722615859128 ""}
|
||||||
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|
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|
||||||
|
<?xml version="1.0" ?>
|
||||||
|
<LOG_ROOT>
|
||||||
|
<PROJECT NAME="test">
|
||||||
|
</PROJECT>
|
||||||
|
</LOG_ROOT>
|
||||||
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|
@ -0,0 +1,52 @@
|
||||||
|
v1
|
||||||
|
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
|
||||||
|
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
|
||||||
|
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||||
|
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||||
|
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||||
|
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||||
|
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
|
||||||
|
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
||||||
|
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
|
||||||
|
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
||||||
|
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
|
||||||
|
IO_RULES_MATRIX,Total Pass,10;0;10;0;0;10;10;0;10;10;0;8;0;0;2;0;8;2;0;0;0;8;0;0;0;0;0;10;0;0,
|
||||||
|
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||||
|
IO_RULES_MATRIX,Total Inapplicable,0;10;0;10;10;0;0;10;0;0;10;2;10;10;8;10;2;8;10;10;10;2;10;10;10;10;10;0;10;10,
|
||||||
|
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||||
|
IO_RULES_MATRIX,a2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a4,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a5,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a6,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a7,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a8,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a9,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,rst_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||||
|
IO_RULES_SUMMARY,Total I/O Rules,30,
|
||||||
|
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
|
||||||
|
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||||
|
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
|
||||||
|
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
|
||||||
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|
|
@ -0,0 +1,3 @@
|
||||||
|
Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
Version_Index = 318808576
|
||||||
|
Creation_Time = Sat Aug 03 00:22:46 2024
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1722615853471 ""}
|
||||||
|
{ "Info" "IMPP_MPP_USER_DEVICE" "test EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1722615853482 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722615853513 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722615853514 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722615853514 ""}
|
||||||
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1722615853565 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722615853793 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722615853793 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722615853793 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1722615853793 ""}
|
||||||
|
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 101 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615853794 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 103 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615853794 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 105 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615853794 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 107 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615853794 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 109 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722615853794 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1722615853794 ""}
|
||||||
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1722615853795 ""}
|
||||||
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1722615854304 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1722615854304 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1722615854305 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1722615854305 ""}
|
||||||
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1722615854306 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722615854311 ""} } { { "../test_top.v" "" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 2 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 96 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722615854311 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "div_clk:div_clk_inst\|clk_div " "Automatically promoted node div_clk:div_clk_inst\|clk_div " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722615854312 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "div_clk:div_clk_inst\|clk_div~0 " "Destination node div_clk:div_clk_inst\|clk_div~0" { } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/test/div_clk.v" 1 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { div_clk:div_clk_inst|clk_div~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 48 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1722615854312 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1722615854312 ""} } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/test/div_clk.v" 1 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { div_clk:div_clk_inst|clk_div } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 25 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722615854312 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node rst_n~input (placed in PIN M1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G0 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722615854312 ""} } { { "../test_top.v" "" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 3 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rst_n~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 0 { 0 ""} 0 95 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722615854312 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1722615854506 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1722615854506 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1722615854507 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1722615854507 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1722615854507 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1722615854508 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1722615854508 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1722615854508 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1722615854518 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1722615854519 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1722615854519 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615854528 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1722615854917 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615854957 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1722615854963 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1722615855345 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615855346 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1722615855547 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y12 X10_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24" { } { { "loc" "" { Generic "E:/FPGA/FPGA_lib/test/par/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24"} 0 12 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1722615855847 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1722615855847 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615856041 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1722615856041 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1722615856041 ""}
|
||||||
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1722615856045 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1722615856092 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1722615856196 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1722615856238 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1722615856355 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722615856622 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/FPGA_lib/test/par/output_files/test.fit.smsg " "Generated suppressed messages file E:/FPGA/FPGA_lib/test/par/output_files/test.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1722615857013 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5874 " "Peak virtual memory: 5874 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615857238 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:24:17 2024 " "Processing ended: Sat Aug 03 00:24:17 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615857238 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615857238 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615857238 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1722615857238 ""}
|
||||||
|
|
@ -0,0 +1,39 @@
|
||||||
|
|test_top
|
||||||
|
clk => clk.IN1
|
||||||
|
rst_n => rst_n.IN1
|
||||||
|
a2 <= a2~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a3 <= a3~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a4 <= a4~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a5 <= a5~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a6 <= a6~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a7 <= a7~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a8 <= a8~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
a9 <= a9~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
||||||
|
|
||||||
|
|test_top|div_clk:div_clk_inst
|
||||||
|
clk => clk_div~reg0.CLK
|
||||||
|
clk => count[0].CLK
|
||||||
|
clk => count[1].CLK
|
||||||
|
clk => count[2].CLK
|
||||||
|
clk => count[3].CLK
|
||||||
|
clk => count[4].CLK
|
||||||
|
clk => count[5].CLK
|
||||||
|
clk => count[6].CLK
|
||||||
|
clk => count[7].CLK
|
||||||
|
clk => count[8].CLK
|
||||||
|
clk => count[9].CLK
|
||||||
|
rst_n => clk_div~reg0.ACLR
|
||||||
|
rst_n => count[0].ACLR
|
||||||
|
rst_n => count[1].ACLR
|
||||||
|
rst_n => count[2].ACLR
|
||||||
|
rst_n => count[3].ACLR
|
||||||
|
rst_n => count[4].ACLR
|
||||||
|
rst_n => count[5].ACLR
|
||||||
|
rst_n => count[6].ACLR
|
||||||
|
rst_n => count[7].ACLR
|
||||||
|
rst_n => count[8].ACLR
|
||||||
|
rst_n => count[9].ACLR
|
||||||
|
clk_div <= clk_div~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
||||||
|
|
||||||
Binary file not shown.
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|
|
@ -0,0 +1,34 @@
|
||||||
|
<TABLE>
|
||||||
|
<TR bgcolor="#C0C0C0">
|
||||||
|
<TH>Hierarchy</TH>
|
||||||
|
<TH>Input</TH>
|
||||||
|
<TH>Constant Input</TH>
|
||||||
|
<TH>Unused Input</TH>
|
||||||
|
<TH>Floating Input</TH>
|
||||||
|
<TH>Output</TH>
|
||||||
|
<TH>Constant Output</TH>
|
||||||
|
<TH>Unused Output</TH>
|
||||||
|
<TH>Floating Output</TH>
|
||||||
|
<TH>Bidir</TH>
|
||||||
|
<TH>Constant Bidir</TH>
|
||||||
|
<TH>Unused Bidir</TH>
|
||||||
|
<TH>Input only Bidir</TH>
|
||||||
|
<TH>Output only Bidir</TH>
|
||||||
|
</TR>
|
||||||
|
<TR >
|
||||||
|
<TD >div_clk_inst</TD>
|
||||||
|
<TD >2</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
</TR>
|
||||||
|
</TABLE>
|
||||||
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|
|
@ -0,0 +1,7 @@
|
||||||
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Legal Partition Candidates ;
|
||||||
|
+--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||||
|
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||||
|
+--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||||
|
; div_clk_inst ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||||
|
+--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||||
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|
|
@ -0,0 +1 @@
|
||||||
|
v1
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1722615851035 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615851036 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:24:10 2024 " "Processing started: Sat Aug 03 00:24:10 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615851036 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1722615851036 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1722615851036 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1722615851379 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/test/test_top.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/test/test_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_top " "Found entity 1: test_top" { } { { "../test_top.v" "" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722615851419 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722615851419 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga/fpga_lib/test/div_clk.v 1 1 " "Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/test/div_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_clk " "Found entity 1: div_clk" { } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/test/div_clk.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1722615851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1722615851420 ""}
|
||||||
|
{ "Info" "ISGN_START_ELABORATION_TOP" "test_top " "Elaborating entity \"test_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1722615851444 ""}
|
||||||
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_clk div_clk:div_clk_inst " "Elaborating entity \"div_clk\" for hierarchy \"div_clk:div_clk_inst\"" { } { { "../test_top.v" "div_clk_inst" { Text "E:/FPGA/FPGA_lib/test/test_top.v" 22 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1722615851452 ""}
|
||||||
|
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1722615851833 ""}
|
||||||
|
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1722615851995 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1722615851995 ""}
|
||||||
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "43 " "Implemented 43 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1722615852018 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1722615852018 ""} { "Info" "ICUT_CUT_TM_LCELLS" "33 " "Implemented 33 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1722615852018 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1722615852018 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615852037 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:24:12 2024 " "Processing ended: Sat Aug 03 00:24:12 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615852037 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615852037 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615852037 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1722615852037 ""}
|
||||||
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|
|
@ -0,0 +1 @@
|
||||||
|
v1
|
||||||
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|
|
@ -0,0 +1 @@
|
||||||
|
DONE
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1722615860420 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860421 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 03 00:24:20 2024 " "Processing started: Sat Aug 03 00:24:20 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1722615860421 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1722615860421 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta test -c test " "Command: quartus_sta test -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1722615860421 ""}
|
||||||
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1722615860523 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1722615860696 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1722615860697 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1722615860730 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1722615860730 ""}
|
||||||
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1722615860891 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1722615860892 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name div_clk:div_clk_inst\|clk_div div_clk:div_clk_inst\|clk_div " "create_clock -period 1.000 -name div_clk:div_clk_inst\|clk_div div_clk:div_clk_inst\|clk_div" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860892 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860892 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860892 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1722615860960 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860960 ""}
|
||||||
|
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1722615860961 ""}
|
||||||
|
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1722615860966 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1722615860973 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1722615860973 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.975 " "Worst-case setup slack is -1.975" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860975 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860975 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.975 -15.066 clk " " -1.975 -15.066 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860975 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.342 -8.886 div_clk:div_clk_inst\|clk_div " " -1.342 -8.886 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860975 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615860975 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.029 " "Worst-case hold slack is 0.029" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860977 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860977 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.029 0.000 clk " " 0.029 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860977 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.464 0.000 div_clk:div_clk_inst\|clk_div " " 0.464 0.000 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860977 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615860977 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615860979 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615860980 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -19.357 clk " " -3.000 -19.357 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -23.792 div_clk:div_clk_inst\|clk_div " " -1.487 -23.792 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615860982 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615860982 ""}
|
||||||
|
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1722615861007 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1722615861025 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1722615861207 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861242 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1722615861246 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1722615861246 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.769 " "Worst-case setup slack is -1.769" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.769 -12.679 clk " " -1.769 -12.679 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.095 -6.926 div_clk:div_clk_inst\|clk_div " " -1.095 -6.926 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861248 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615861248 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.114 " "Worst-case hold slack is 0.114" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.114 0.000 clk " " 0.114 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.416 0.000 div_clk:div_clk_inst\|clk_div " " 0.416 0.000 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861250 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615861250 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615861253 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615861255 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -19.357 clk " " -3.000 -19.357 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -23.792 div_clk:div_clk_inst\|clk_div " " -1.487 -23.792 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861257 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615861257 ""}
|
||||||
|
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1722615861286 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861416 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1722615861417 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1722615861417 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.231 " "Worst-case setup slack is -0.231" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861420 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861420 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.231 -0.813 clk " " -0.231 -0.813 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861420 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.022 -0.022 div_clk:div_clk_inst\|clk_div " " -0.022 -0.022 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861420 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615861420 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.129 " "Worst-case hold slack is -0.129" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.129 -0.129 clk " " -0.129 -0.129 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 div_clk:div_clk_inst\|clk_div " " 0.193 0.000 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861423 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615861423 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615861427 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1722615861430 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.715 clk " " -3.000 -14.715 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -16.000 div_clk:div_clk_inst\|clk_div " " -1.000 -16.000 div_clk:div_clk_inst\|clk_div " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1722615861432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1722615861432 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1722615861716 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1722615861716 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4762 " "Peak virtual memory: 4762 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722615861770 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 03 00:24:21 2024 " "Processing ended: Sat Aug 03 00:24:21 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722615861770 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722615861770 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722615861770 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1722615861770 ""}
|
||||||
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|
|
@ -0,0 +1,6 @@
|
||||||
|
start_full_compilation:s:00:00:12
|
||||||
|
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||||
|
start_analysis_elaboration:s-start_full_compilation
|
||||||
|
start_fitter:s:00:00:05-start_full_compilation
|
||||||
|
start_assembler:s:00:00:02-start_full_compilation
|
||||||
|
start_timing_analyzer:s:00:00:03-start_full_compilation
|
||||||
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|
|
@ -0,0 +1,11 @@
|
||||||
|
This folder contains data for incremental compilation.
|
||||||
|
|
||||||
|
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||||
|
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||||
|
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||||
|
the db and incremental_db folder should be removed.
|
||||||
|
|
||||||
|
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||||
|
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||||
|
when the db or incremental_db/compiled_partitions folders are removed.
|
||||||
|
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
Version_Index = 318808576
|
||||||
|
Creation_Time = Sat Aug 03 00:04:25 2024
|
||||||
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|
|
@ -0,0 +1 @@
|
||||||
|
v1
|
||||||
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|
|
@ -0,0 +1 @@
|
||||||
|
c5eb7f6cdd530884c3b884e0a3668ea4
|
||||||
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|
|
@ -0,0 +1,13 @@
|
||||||
|
/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
|
||||||
|
JedecChain;
|
||||||
|
FileRevision(JESD32A);
|
||||||
|
DefaultMfr(6E);
|
||||||
|
|
||||||
|
P ActionCode(Cfg)
|
||||||
|
Device PartName(EP4CE10F17) Path("E:/FPGA/FPGA_lib/test/par/output_files/") File("test.sof") MfrSpec(OpMask(1));
|
||||||
|
|
||||||
|
ChainEnd;
|
||||||
|
|
||||||
|
AlteraBegin;
|
||||||
|
ChainType(JTAG);
|
||||||
|
AlteraEnd;
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
Assembler report for test
|
||||||
|
Sat Aug 03 00:24:19 2024
|
||||||
|
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
|
||||||
|
; Table of Contents ;
|
||||||
|
---------------------
|
||||||
|
1. Legal Notice
|
||||||
|
2. Assembler Summary
|
||||||
|
3. Assembler Settings
|
||||||
|
4. Assembler Generated Files
|
||||||
|
5. Assembler Device Options: E:/FPGA/FPGA_lib/test/par/output_files/test.sof
|
||||||
|
6. Assembler Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and its AMPP partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Altera Program License
|
||||||
|
Subscription Agreement, Altera MegaCore Function License
|
||||||
|
Agreement, or other applicable license agreement, including,
|
||||||
|
without limitation, that your use is for the sole purpose of
|
||||||
|
programming logic devices manufactured by Altera and sold by
|
||||||
|
Altera or its authorized distributors. Please refer to the
|
||||||
|
applicable agreement for further details.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------+
|
||||||
|
; Assembler Summary ;
|
||||||
|
+-----------------------+---------------------------------------+
|
||||||
|
; Assembler Status ; Successful - Sat Aug 03 00:24:19 2024 ;
|
||||||
|
; Revision Name ; test ;
|
||||||
|
; Top-level Entity Name ; test_top ;
|
||||||
|
; Family ; Cyclone IV E ;
|
||||||
|
; Device ; EP4CE10F17C8 ;
|
||||||
|
+-----------------------+---------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------------------------------------------------------------+
|
||||||
|
; Assembler Settings ;
|
||||||
|
+-----------------------------------------------------------------------------+----------+---------------+
|
||||||
|
; Option ; Setting ; Default Value ;
|
||||||
|
+-----------------------------------------------------------------------------+----------+---------------+
|
||||||
|
; Use smart compilation ; Off ; Off ;
|
||||||
|
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||||
|
; Enable compact report table ; Off ; Off ;
|
||||||
|
; Generate compressed bitstreams ; On ; On ;
|
||||||
|
; Compression mode ; Off ; Off ;
|
||||||
|
; Clock source for configuration device ; Internal ; Internal ;
|
||||||
|
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
||||||
|
; Divide clock frequency by ; 1 ; 1 ;
|
||||||
|
; Auto user code ; On ; On ;
|
||||||
|
; Use configuration device ; Off ; Off ;
|
||||||
|
; Configuration device ; Auto ; Auto ;
|
||||||
|
; Configuration device auto user code ; Off ; Off ;
|
||||||
|
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
||||||
|
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
||||||
|
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
||||||
|
; Hexadecimal Output File start address ; 0 ; 0 ;
|
||||||
|
; Hexadecimal Output File count direction ; Up ; Up ;
|
||||||
|
; Release clears before tri-states ; Off ; Off ;
|
||||||
|
; Auto-restart configuration after error ; On ; On ;
|
||||||
|
; Enable OCT_DONE ; Off ; Off ;
|
||||||
|
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
||||||
|
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
||||||
|
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
||||||
|
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
||||||
|
+-----------------------------------------------------------------------------+----------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------------------------+
|
||||||
|
; Assembler Generated Files ;
|
||||||
|
+-------------------------------------------------+
|
||||||
|
; File Name ;
|
||||||
|
+-------------------------------------------------+
|
||||||
|
; E:/FPGA/FPGA_lib/test/par/output_files/test.sof ;
|
||||||
|
+-------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------------------+
|
||||||
|
; Assembler Device Options: E:/FPGA/FPGA_lib/test/par/output_files/test.sof ;
|
||||||
|
+----------------+----------------------------------------------------------+
|
||||||
|
; Option ; Setting ;
|
||||||
|
+----------------+----------------------------------------------------------+
|
||||||
|
; Device ; EP4CE10F17C8 ;
|
||||||
|
; JTAG usercode ; 0x0008B5F5 ;
|
||||||
|
; Checksum ; 0x0008B5F5 ;
|
||||||
|
+----------------+----------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------+
|
||||||
|
; Assembler Messages ;
|
||||||
|
+--------------------+
|
||||||
|
Info: *******************************************************************
|
||||||
|
Info: Running Quartus II 64-Bit Assembler
|
||||||
|
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
Info: Processing started: Sat Aug 03 00:24:18 2024
|
||||||
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off test -c test
|
||||||
|
Info (115031): Writing out detailed assembly data for power analysis
|
||||||
|
Info (115030): Assembler is generating device programming files
|
||||||
|
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
||||||
|
Info: Peak virtual memory: 4590 megabytes
|
||||||
|
Info: Processing ended: Sat Aug 03 00:24:19 2024
|
||||||
|
Info: Elapsed time: 00:00:01
|
||||||
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1 @@
|
||||||
|
Sat Aug 03 00:24:22 2024
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,8 @@
|
||||||
|
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||||
|
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||||
|
Extra Info (176236): Started Fast Input/Output/OE register processing
|
||||||
|
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||||
|
Extra Info (176238): Start inferring scan chains for DSP blocks
|
||||||
|
Extra Info (176239): Inferring scan chains for DSP blocks is complete
|
||||||
|
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||||
|
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
Fitter Status : Successful - Sat Aug 03 00:24:16 2024
|
||||||
|
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
Revision Name : test
|
||||||
|
Top-level Entity Name : test_top
|
||||||
|
Family : Cyclone IV E
|
||||||
|
Device : EP4CE10F17C8
|
||||||
|
Timing Models : Final
|
||||||
|
Total logic elements : 34 / 10,320 ( < 1 % )
|
||||||
|
Total combinational functions : 25 / 10,320 ( < 1 % )
|
||||||
|
Dedicated logic registers : 27 / 10,320 ( < 1 % )
|
||||||
|
Total registers : 27
|
||||||
|
Total pins : 10 / 180 ( 6 % )
|
||||||
|
Total virtual pins : 0
|
||||||
|
Total memory bits : 0 / 423,936 ( 0 % )
|
||||||
|
Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % )
|
||||||
|
Total PLLs : 0 / 2 ( 0 % )
|
||||||
|
|
@ -0,0 +1,124 @@
|
||||||
|
Flow report for test
|
||||||
|
Sat Aug 03 00:24:21 2024
|
||||||
|
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
|
||||||
|
; Table of Contents ;
|
||||||
|
---------------------
|
||||||
|
1. Legal Notice
|
||||||
|
2. Flow Summary
|
||||||
|
3. Flow Settings
|
||||||
|
4. Flow Non-Default Global Settings
|
||||||
|
5. Flow Elapsed Time
|
||||||
|
6. Flow OS Summary
|
||||||
|
7. Flow Log
|
||||||
|
8. Flow Messages
|
||||||
|
9. Flow Suppressed Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and its AMPP partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Altera Program License
|
||||||
|
Subscription Agreement, Altera MegaCore Function License
|
||||||
|
Agreement, or other applicable license agreement, including,
|
||||||
|
without limitation, that your use is for the sole purpose of
|
||||||
|
programming logic devices manufactured by Altera and sold by
|
||||||
|
Altera or its authorized distributors. Please refer to the
|
||||||
|
applicable agreement for further details.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+----------------------------------------------------------------------------------+
|
||||||
|
; Flow Summary ;
|
||||||
|
+------------------------------------+---------------------------------------------+
|
||||||
|
; Flow Status ; Successful - Sat Aug 03 00:24:19 2024 ;
|
||||||
|
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
|
||||||
|
; Revision Name ; test ;
|
||||||
|
; Top-level Entity Name ; test_top ;
|
||||||
|
; Family ; Cyclone IV E ;
|
||||||
|
; Device ; EP4CE10F17C8 ;
|
||||||
|
; Timing Models ; Final ;
|
||||||
|
; Total logic elements ; 34 / 10,320 ( < 1 % ) ;
|
||||||
|
; Total combinational functions ; 25 / 10,320 ( < 1 % ) ;
|
||||||
|
; Dedicated logic registers ; 27 / 10,320 ( < 1 % ) ;
|
||||||
|
; Total registers ; 27 ;
|
||||||
|
; Total pins ; 10 / 180 ( 6 % ) ;
|
||||||
|
; Total virtual pins ; 0 ;
|
||||||
|
; Total memory bits ; 0 / 423,936 ( 0 % ) ;
|
||||||
|
; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ;
|
||||||
|
; Total PLLs ; 0 / 2 ( 0 % ) ;
|
||||||
|
+------------------------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-----------------------------------------+
|
||||||
|
; Flow Settings ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
; Option ; Setting ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
; Start date & time ; 08/03/2024 00:24:11 ;
|
||||||
|
; Main task ; Compilation ;
|
||||||
|
; Revision Name ; test ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Flow Non-Default Global Settings ;
|
||||||
|
+-------------------------------------+------------------------------+---------------+-------------+------------+
|
||||||
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
|
+-------------------------------------+------------------------------+---------------+-------------+------------+
|
||||||
|
; COMPILER_SIGNATURE_ID ; 929351042773.172261585120392 ; -- ; -- ; -- ;
|
||||||
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||||
|
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
|
||||||
|
; PARTITION_COLOR ; 16764057 ; -- ; test_top ; Top ;
|
||||||
|
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; test_top ; Top ;
|
||||||
|
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; test_top ; Top ;
|
||||||
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||||
|
; TOP_LEVEL_ENTITY ; test_top ; test ; -- ; -- ;
|
||||||
|
+-------------------------------------+------------------------------+---------------+-------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Flow Elapsed Time ;
|
||||||
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:01 ;
|
||||||
|
; Fitter ; 00:00:04 ; 1.0 ; 5874 MB ; 00:00:05 ;
|
||||||
|
; Assembler ; 00:00:01 ; 1.0 ; 4582 MB ; 00:00:01 ;
|
||||||
|
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4762 MB ; 00:00:02 ;
|
||||||
|
; Total ; 00:00:07 ; -- ; -- ; 00:00:09 ;
|
||||||
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+----------------------------------------------------------------------------------------+
|
||||||
|
; Flow OS Summary ;
|
||||||
|
+---------------------------+------------------+-----------+------------+----------------+
|
||||||
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||||
|
+---------------------------+------------------+-----------+------------+----------------+
|
||||||
|
; Analysis & Synthesis ; DESKTOP-VU2RK6T ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
|
; Fitter ; DESKTOP-VU2RK6T ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
|
; Assembler ; DESKTOP-VU2RK6T ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
|
; TimeQuest Timing Analyzer ; DESKTOP-VU2RK6T ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
|
+---------------------------+------------------+-----------+------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
|
------------
|
||||||
|
; Flow Log ;
|
||||||
|
------------
|
||||||
|
quartus_map --read_settings_files=on --write_settings_files=off test -c test
|
||||||
|
quartus_fit --read_settings_files=off --write_settings_files=off test -c test
|
||||||
|
quartus_asm --read_settings_files=off --write_settings_files=off test -c test
|
||||||
|
quartus_sta test -c test
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,8 @@
|
||||||
|
<sld_project_info>
|
||||||
|
<project>
|
||||||
|
<hash md5_digest_80b="ab5557854ccc8d571df5"/>
|
||||||
|
</project>
|
||||||
|
<file_info>
|
||||||
|
<file device="EP4CE10F17C8" path="test.sof" usercode="0xFFFFFFFF"/>
|
||||||
|
</file_info>
|
||||||
|
</sld_project_info>
|
||||||
|
|
@ -0,0 +1,280 @@
|
||||||
|
Analysis & Synthesis report for test
|
||||||
|
Sat Aug 03 00:24:12 2024
|
||||||
|
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
|
||||||
|
; Table of Contents ;
|
||||||
|
---------------------
|
||||||
|
1. Legal Notice
|
||||||
|
2. Analysis & Synthesis Summary
|
||||||
|
3. Analysis & Synthesis Settings
|
||||||
|
4. Parallel Compilation
|
||||||
|
5. Analysis & Synthesis Source Files Read
|
||||||
|
6. Analysis & Synthesis Resource Usage Summary
|
||||||
|
7. Analysis & Synthesis Resource Utilization by Entity
|
||||||
|
8. General Register Statistics
|
||||||
|
9. Parameter Settings for User Entity Instance: div_clk:div_clk_inst
|
||||||
|
10. Elapsed Time Per Partition
|
||||||
|
11. Analysis & Synthesis Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and its AMPP partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Altera Program License
|
||||||
|
Subscription Agreement, Altera MegaCore Function License
|
||||||
|
Agreement, or other applicable license agreement, including,
|
||||||
|
without limitation, that your use is for the sole purpose of
|
||||||
|
programming logic devices manufactured by Altera and sold by
|
||||||
|
Altera or its authorized distributors. Please refer to the
|
||||||
|
applicable agreement for further details.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+----------------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Summary ;
|
||||||
|
+------------------------------------+---------------------------------------------+
|
||||||
|
; Analysis & Synthesis Status ; Successful - Sat Aug 03 00:24:12 2024 ;
|
||||||
|
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
|
||||||
|
; Revision Name ; test ;
|
||||||
|
; Top-level Entity Name ; test_top ;
|
||||||
|
; Family ; Cyclone IV E ;
|
||||||
|
; Total logic elements ; 33 ;
|
||||||
|
; Total combinational functions ; 25 ;
|
||||||
|
; Dedicated logic registers ; 27 ;
|
||||||
|
; Total registers ; 27 ;
|
||||||
|
; Total pins ; 10 ;
|
||||||
|
; Total virtual pins ; 0 ;
|
||||||
|
; Total memory bits ; 0 ;
|
||||||
|
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||||
|
; Total PLLs ; 0 ;
|
||||||
|
+------------------------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+----------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Settings ;
|
||||||
|
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
; Option ; Setting ; Default Value ;
|
||||||
|
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
; Device ; EP4CE10F17C8 ; ;
|
||||||
|
; Top-level entity name ; test_top ; test ;
|
||||||
|
; Family name ; Cyclone IV E ; Cyclone IV GX ;
|
||||||
|
; Use smart compilation ; Off ; Off ;
|
||||||
|
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||||
|
; Enable compact report table ; Off ; Off ;
|
||||||
|
; Restructure Multiplexers ; Auto ; Auto ;
|
||||||
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||||
|
; Preserve fewer node names ; On ; On ;
|
||||||
|
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
||||||
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||||
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||||
|
; State Machine Processing ; Auto ; Auto ;
|
||||||
|
; Safe State Machine ; Off ; Off ;
|
||||||
|
; Extract Verilog State Machines ; On ; On ;
|
||||||
|
; Extract VHDL State Machines ; On ; On ;
|
||||||
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||||
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||||
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||||
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||||
|
; Infer RAMs from Raw Logic ; On ; On ;
|
||||||
|
; Parallel Synthesis ; On ; On ;
|
||||||
|
; DSP Block Balancing ; Auto ; Auto ;
|
||||||
|
; NOT Gate Push-Back ; On ; On ;
|
||||||
|
; Power-Up Don't Care ; On ; On ;
|
||||||
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||||
|
; Remove Duplicate Registers ; On ; On ;
|
||||||
|
; Ignore CARRY Buffers ; Off ; Off ;
|
||||||
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||||
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||||
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||||
|
; Ignore LCELL Buffers ; Off ; Off ;
|
||||||
|
; Ignore SOFT Buffers ; On ; On ;
|
||||||
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||||
|
; Optimization Technique ; Balanced ; Balanced ;
|
||||||
|
; Carry Chain Length ; 70 ; 70 ;
|
||||||
|
; Auto Carry Chains ; On ; On ;
|
||||||
|
; Auto Open-Drain Pins ; On ; On ;
|
||||||
|
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||||
|
; Auto ROM Replacement ; On ; On ;
|
||||||
|
; Auto RAM Replacement ; On ; On ;
|
||||||
|
; Auto DSP Block Replacement ; On ; On ;
|
||||||
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||||
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||||
|
; Auto Clock Enable Replacement ; On ; On ;
|
||||||
|
; Strict RAM Replacement ; Off ; Off ;
|
||||||
|
; Allow Synchronous Control Signals ; On ; On ;
|
||||||
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||||
|
; Auto RAM Block Balancing ; On ; On ;
|
||||||
|
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
|
||||||
|
; Auto Resource Sharing ; Off ; Off ;
|
||||||
|
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
||||||
|
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
||||||
|
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
||||||
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||||
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||||
|
; Timing-Driven Synthesis ; On ; On ;
|
||||||
|
; Report Parameter Settings ; On ; On ;
|
||||||
|
; Report Source Assignments ; On ; On ;
|
||||||
|
; Report Connectivity Checks ; On ; On ;
|
||||||
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||||
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||||
|
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
||||||
|
; HDL message level ; Level2 ; Level2 ;
|
||||||
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||||
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||||
|
; Clock MUX Protection ; On ; On ;
|
||||||
|
; Auto Gated Clock Conversion ; Off ; Off ;
|
||||||
|
; Block Design Naming ; Auto ; Auto ;
|
||||||
|
; SDC constraint protection ; Off ; Off ;
|
||||||
|
; Synthesis Effort ; Auto ; Auto ;
|
||||||
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||||
|
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
||||||
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||||
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||||
|
; Resource Aware Inference For Block RAM ; On ; On ;
|
||||||
|
; Synthesis Seed ; 1 ; 1 ;
|
||||||
|
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------+
|
||||||
|
; Parallel Compilation ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
; Processors ; Number ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
; Number detected on machine ; 12 ;
|
||||||
|
; Maximum allowed ; 12 ;
|
||||||
|
; ; ;
|
||||||
|
; Average used ; 1.00 ;
|
||||||
|
; Maximum used ; 1 ;
|
||||||
|
; ; ;
|
||||||
|
; Usage by Processor ; % Time Used ;
|
||||||
|
; Processor 1 ; 100.0% ;
|
||||||
|
; Processors 2-12 ; 0.0% ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Source Files Read ;
|
||||||
|
+----------------------------------+-----------------+------------------------+----------------------------------+---------+
|
||||||
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||||
|
+----------------------------------+-----------------+------------------------+----------------------------------+---------+
|
||||||
|
; ../test_top.v ; yes ; User Verilog HDL File ; E:/FPGA/FPGA_lib/test/test_top.v ; ;
|
||||||
|
; ../div_clk.v ; yes ; User Verilog HDL File ; E:/FPGA/FPGA_lib/test/div_clk.v ; ;
|
||||||
|
+----------------------------------+-----------------+------------------------+----------------------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
|
+-----------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Resource Usage Summary ;
|
||||||
|
+---------------------------------------------+-------------+
|
||||||
|
; Resource ; Usage ;
|
||||||
|
+---------------------------------------------+-------------+
|
||||||
|
; Estimated Total logic elements ; 33 ;
|
||||||
|
; ; ;
|
||||||
|
; Total combinational functions ; 25 ;
|
||||||
|
; Logic element usage by number of LUT inputs ; ;
|
||||||
|
; -- 4 input functions ; 3 ;
|
||||||
|
; -- 3 input functions ; 1 ;
|
||||||
|
; -- <=2 input functions ; 21 ;
|
||||||
|
; ; ;
|
||||||
|
; Logic elements by mode ; ;
|
||||||
|
; -- normal mode ; 10 ;
|
||||||
|
; -- arithmetic mode ; 15 ;
|
||||||
|
; ; ;
|
||||||
|
; Total registers ; 27 ;
|
||||||
|
; -- Dedicated logic registers ; 27 ;
|
||||||
|
; -- I/O registers ; 0 ;
|
||||||
|
; ; ;
|
||||||
|
; I/O pins ; 10 ;
|
||||||
|
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||||
|
; Maximum fan-out node ; rst_n~input ;
|
||||||
|
; Maximum fan-out ; 27 ;
|
||||||
|
; Total fan-out ; 153 ;
|
||||||
|
; Average fan-out ; 2.13 ;
|
||||||
|
+---------------------------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||||
|
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
|
||||||
|
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
|
||||||
|
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
|
||||||
|
; |test_top ; 25 (8) ; 27 (16) ; 0 ; 0 ; 0 ; 0 ; 10 ; 0 ; |test_top ; work ;
|
||||||
|
; |div_clk:div_clk_inst| ; 17 (17) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_top|div_clk:div_clk_inst ; work ;
|
||||||
|
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
|
||||||
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------------------+
|
||||||
|
; General Register Statistics ;
|
||||||
|
+----------------------------------------------+-------+
|
||||||
|
; Statistic ; Value ;
|
||||||
|
+----------------------------------------------+-------+
|
||||||
|
; Total registers ; 27 ;
|
||||||
|
; Number of registers using Synchronous Clear ; 0 ;
|
||||||
|
; Number of registers using Synchronous Load ; 0 ;
|
||||||
|
; Number of registers using Asynchronous Clear ; 27 ;
|
||||||
|
; Number of registers using Asynchronous Load ; 0 ;
|
||||||
|
; Number of registers using Clock Enable ; 0 ;
|
||||||
|
; Number of registers using Preset ; 0 ;
|
||||||
|
+----------------------------------------------+-------+
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------------------------------------------+
|
||||||
|
; Parameter Settings for User Entity Instance: div_clk:div_clk_inst ;
|
||||||
|
+----------------+-------+------------------------------------------+
|
||||||
|
; Parameter Name ; Value ; Type ;
|
||||||
|
+----------------+-------+------------------------------------------+
|
||||||
|
; DIV ; 50 ; Signed Integer ;
|
||||||
|
; COUNT_WITH ; 10 ; Signed Integer ;
|
||||||
|
+----------------+-------+------------------------------------------+
|
||||||
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------+
|
||||||
|
; Elapsed Time Per Partition ;
|
||||||
|
+----------------+--------------+
|
||||||
|
; Partition Name ; Elapsed Time ;
|
||||||
|
+----------------+--------------+
|
||||||
|
; Top ; 00:00:00 ;
|
||||||
|
+----------------+--------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------+
|
||||||
|
; Analysis & Synthesis Messages ;
|
||||||
|
+-------------------------------+
|
||||||
|
Info: *******************************************************************
|
||||||
|
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
||||||
|
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||||||
|
Info: Processing started: Sat Aug 03 00:24:10 2024
|
||||||
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
|
||||||
|
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
|
||||||
|
Info (12021): Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/test/test_top.v
|
||||||
|
Info (12023): Found entity 1: test_top
|
||||||
|
Info (12021): Found 1 design units, including 1 entities, in source file /fpga/fpga_lib/test/div_clk.v
|
||||||
|
Info (12023): Found entity 1: div_clk
|
||||||
|
Info (12127): Elaborating entity "test_top" for the top level hierarchy
|
||||||
|
Info (12128): Elaborating entity "div_clk" for hierarchy "div_clk:div_clk_inst"
|
||||||
|
Info (286030): Timing-Driven Synthesis is running
|
||||||
|
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||||
|
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||||
|
Info (21057): Implemented 43 device resources after synthesis - the final resource count might be different
|
||||||
|
Info (21058): Implemented 2 input pins
|
||||||
|
Info (21059): Implemented 8 output pins
|
||||||
|
Info (21061): Implemented 33 logic cells
|
||||||
|
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
|
||||||
|
Info: Peak virtual memory: 4662 megabytes
|
||||||
|
Info: Processing ended: Sat Aug 03 00:24:12 2024
|
||||||
|
Info: Elapsed time: 00:00:02
|
||||||
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue